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path: root/src/aig/gia
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* Experiment with partitioned &scorr.Alan Mishchenko2019-01-151-0/+185
* Adding one API of GIA manager.Alan Mishchenko2019-01-121-0/+18
* Bug fix in deriving names for the miter output.Alan Mishchenko2019-01-101-4/+9
* Fixing float overflow during area-flow computation in &lf.Alan Mishchenko2018-12-131-0/+8
* Adding switch &w -n to modify the comment section of the AIGER file written.Alan Mishchenko2018-11-2110-17/+16
* Adding an option to write new-line after the comment symbol when dumping an A...Alan Mishchenko2018-11-201-2/+7
* Undoing some of the previous changes.Alan Mishchenko2018-11-151-1/+5
* Procedures to verify equivalence classes.Alan Mishchenko2018-11-111-1/+139
* Several recent bug fixes.Alan Mishchenko2018-11-041-3/+2
* Fix timing info communication in GIA APIs.Alan Mishchenko2018-10-231-0/+1
* Fix timing info communication in GIA APIs.Alan Mishchenko2018-10-231-0/+1
* Fix timing info communication in GIA APIs.Alan Mishchenko2018-10-222-1/+27
* Preserving output names while deriving a miter.Alan Mishchenko2018-09-201-0/+26
* Preserving names while deriving a miter.Alan Mishchenko2018-09-201-0/+2
* Procedure to return seq equivalences.Alan Mishchenko2018-07-221-0/+68
* Compiler warnings.Alan Mishchenko2018-06-081-1/+2
* Supporting the decoder primitive in NDR and bit-blasting.Alan Mishchenko2018-06-051-1/+1
* Disabling unused feature in &nf.Alan Mishchenko2018-06-041-0/+2
* Adding switch &w -p to dump AIG in a Verilog file.Alan Mishchenko2018-04-252-0/+186
* Making sure duplicated inverters are not created.Alan Mishchenko2018-04-111-3/+9
* Integrating SAT-based CEX minimization (bug fix).Alan Mishchenko2018-03-251-4/+8
* Integrating SAT-based CEX minimization.Alan Mishchenko2018-03-251-2/+106
* Updating &mfs to support hard objects.Alan Mishchenko2018-03-231-2/+25
* Adding parameters and improvements to %blast.Alan Mishchenko2018-02-281-3/+3
* Improvements to circuit based solver.Alan Mishchenko2018-02-201-33/+81
* Improvements to circuit based solver.Alan Mishchenko2018-02-171-193/+490
* Extending MiniLUT to return attributes.Alan Mishchenko2018-02-111-0/+19
* Experiments with LUT mapping.Alan Mishchenko2018-02-102-9/+47
* Experiments with circuit-based SAT.Alan Mishchenko2018-01-271-26/+225
* Experiments with circuit-based SAT.Alan Mishchenko2018-01-271-132/+94
* Experiments with circuit-based SAT.Alan Mishchenko2018-01-271-31/+38
* Experiments with circuit-based SAT.Alan Mishchenko2018-01-271-130/+161
* Experiments with circuit-based SAT.Alan Mishchenko2018-01-274-0/+1293
* Experiments with SAT-based simulation.Alan Mishchenko2018-01-253-8/+42
* Experiments with SAT-based simulation.Alan Mishchenko2018-01-233-3/+122
* Fixed crash in &nf when there is no buffer gate.Alan Mishchenko2018-01-121-0/+5
* Corner-case bug fixed in CNF generation.Alan Mishchenko2017-12-281-0/+1
* Corner-case bug fixed in CNF generation.Alan Mishchenko2017-12-281-1/+6
* Experiments with AIG-based simulation.Alan Mishchenko2017-12-053-11/+244
* Portability changes for gcc-6 suggested by Clifford.Alan Mishchenko2017-12-021-6/+4
* Improvements to AIG-based quantification.Alan Mishchenko2017-11-265-247/+548
* C++ compatibility: fix incompatible parameter listBaruch Sterin2017-11-231-1/+1
* C++ compatibility: cast returned void*Baruch Sterin2017-11-231-2/+2
* Experimental CEX minimization code.Alan Mishchenko2017-11-231-0/+116
* Extracting CSAT interface and several cleanups.Alan Mishchenko2017-11-134-10/+26
* Changes to make GIA structural hashing use a dedicated array instead of pObj-...Alan Mishchenko2017-11-135-71/+75
* Improvements to quantification.Alan Mishchenko2017-11-133-0/+251
* Profiling quantification and other changes.Alan Mishchenko2017-11-062-0/+6
* Profiling quantification and other changes.Alan Mishchenko2017-11-064-1/+212
* Improvements to quantification.Alan Mishchenko2017-10-292-0/+80
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