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* MUX decomposition during mapping.Alan Mishchenko2014-10-121-7/+10
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* Recommended changes for portability.Alan Mishchenko2014-10-122-4/+39
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* MUX decomposition during mapping.Alan Mishchenko2014-10-111-25/+121
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* Deriving network in terms of programmable cells.Alan Mishchenko2014-10-111-5/+12
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* Correction to the patch to compile with Visual Studio.Alan Mishchenko2014-10-101-1/+1
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* Suggested patch for type-punned warningsAlan Mishchenko2014-10-102-6/+16
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* Small changes.Alan Mishchenko2014-10-081-8/+8
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* Compiler warnings.Alan Mishchenko2014-10-081-1/+1
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* Detection of threshold functions.Alan Mishchenko2014-10-081-9/+11
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* Updates to &flow and &flow2.Alan Mishchenko2014-10-051-9/+9
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* Deriving cell mapping with &if -kz.Alan Mishchenko2014-10-044-18/+73
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* Deriving AIG after cell mapping.Alan Mishchenko2014-10-031-0/+29
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* Adding options to &flow.Alan Mishchenko2014-09-291-8/+10
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* Adding options to &flow2.Alan Mishchenko2014-09-291-4/+4
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* Adding options to &flow2.Alan Mishchenko2014-09-291-5/+5
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* Adding options to &flow.Alan Mishchenko2014-09-291-17/+17
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* Adding out-of-bounds checks to AIGER readers.Alan Mishchenko2014-09-281-1/+1
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* Adding features to CNF generation.Alan Mishchenko2014-09-281-2/+2
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* Added switch -t to &flow2.Alan Mishchenko2014-09-241-5/+5
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* Extending &cec to take a single-output miter (usage of switch -d has changed!).Alan Mishchenko2014-09-232-0/+26
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* Adding switch to enable SOP balancing in '&flow2'.Alan Mishchenko2014-09-211-10/+21
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* Tuning the flow scripts.Alan Mishchenko2014-09-201-1/+1
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* Tuning the flow scripts.Alan Mishchenko2014-09-201-5/+69
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* Tuning the flow scripts.Alan Mishchenko2014-09-201-124/+173
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* Concurrency for Boolean matching.Alan Mishchenko2014-09-181-2/+10
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* Spurious assertion.Alan Mishchenko2014-09-171-1/+1
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* New choice computation.Alan Mishchenko2014-09-161-3/+123
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* Code restructuring.Alan Mishchenko2014-09-165-316/+373
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* Updating timing info during normalization.Alan Mishchenko2014-09-101-1/+1
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* Updating timing info during normalization.Alan Mishchenko2014-09-101-1/+3
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* Bug fix in transferring timing info.Alan Mishchenko2014-09-091-1/+1
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* Tuning LUT mapping flow.Alan Mishchenko2014-08-281-1/+4
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* Tuning LUT mapping flow.Alan Mishchenko2014-08-271-3/+5
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* Tuning LUT mapping flow.Alan Mishchenko2014-08-271-0/+119
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* Improvements to DSD balancing.Alan Mishchenko2014-08-272-6/+6
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* Adding commands to save/load best network.Alan Mishchenko2014-08-264-2/+176
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* Improvements to the timing manager.Alan Mishchenko2014-08-252-7/+5
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* Improving GIA interfaces for some procedures.Alan Mishchenko2014-08-257-53/+69
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* Correcting incorrect handling of timing in several &-commands.Alan Mishchenko2014-08-255-43/+55
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* Improving print-out of 'dsd -p'.Alan Mishchenko2014-08-221-0/+35
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* Propagating timing support to the new synthesis/mapping commands.Alan Mishchenko2014-08-206-32/+25
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* Extended command &cone to extract timing critical cones.Alan Mishchenko2014-08-192-26/+90
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* Changing default CNF generation in &bmc.Alan Mishchenko2014-08-181-0/+6
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* Added DSD-based collapsing &dsd.Alan Mishchenko2014-08-161-1/+1
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* Added DSD-based collapsing &dsd.Alan Mishchenko2014-08-161-2/+3
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* Added DSD-based collapsing &dsd.Alan Mishchenko2014-08-161-0/+1
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* Added DSD-based collapsing &dsd.Alan Mishchenko2014-08-162-4/+381
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* Increasing the size of pre-allocated memory in &syn2.Alan Mishchenko2014-08-111-1/+1
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* Adding delay optimization to synthesis script &syn2.Alan Mishchenko2014-08-083-4/+84
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* Enabling cofactoring in the mapper.Alan Mishchenko2014-08-061-0/+1
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