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* Adding an option to write new-line after the comment symbol when dumping an A...Alan Mishchenko2018-11-201-2/+7
* Undoing some of the previous changes.Alan Mishchenko2018-11-151-1/+5
* Procedures to verify equivalence classes.Alan Mishchenko2018-11-111-1/+139
* Several recent bug fixes.Alan Mishchenko2018-11-042-4/+3
* Fix timing info communication in GIA APIs.Alan Mishchenko2018-10-231-0/+1
* Fix timing info communication in GIA APIs.Alan Mishchenko2018-10-231-0/+1
* Fix timing info communication in GIA APIs.Alan Mishchenko2018-10-222-1/+27
* Experiments with word-level retiming.Alan Mishchenko2018-09-301-2/+5
* Preserving output names while deriving a miter.Alan Mishchenko2018-09-201-0/+26
* Preserving names while deriving a miter.Alan Mishchenko2018-09-201-0/+2
* Procedure to return seq equivalences.Alan Mishchenko2018-07-221-0/+68
* Extending NDR to support adder/subtractor.Alan Mishchenko2018-06-141-0/+36
* Bug fix (accessing unassigned memory).Alan Mishchenko2018-06-121-1/+7
* Compiler warnings.Alan Mishchenko2018-06-082-3/+4
* Supporting the decoder primitive in NDR and bit-blasting.Alan Mishchenko2018-06-052-1/+33
* Disabling unused feature in &nf.Alan Mishchenko2018-06-041-0/+2
* Supporting NMUX and SEL in NDR.Alan Mishchenko2018-05-241-0/+55
* Updates to NDR format (bug fixes).Alan Mishchenko2018-05-032-21/+29
* Updates to NDR format (flops, memories, signed mult, etc).Alan Mishchenko2018-04-292-61/+244
* Adding switch &w -p to dump AIG in a Verilog file.Alan Mishchenko2018-04-252-0/+186
* Adding adder-subtractor primitive.Alan Mishchenko2018-04-111-1/+3
* Making sure duplicated inverters are not created.Alan Mishchenko2018-04-111-3/+9
* Integrating SAT-based CEX minimization (bug fix).Alan Mishchenko2018-03-251-4/+8
* Integrating SAT-based CEX minimization.Alan Mishchenko2018-03-251-2/+106
* Updating &mfs to support hard objects.Alan Mishchenko2018-03-231-2/+25
* Adding switch 'scorr -f' to dump inductive invariant as an AIG.Alan Mishchenko2018-03-222-2/+4
* Adding parameters and improvements to %blast.Alan Mishchenko2018-02-281-3/+3
* Adding support for adders with carry-in in WLC and NDR.Alan Mishchenko2018-02-241-0/+98
* Improvements to circuit based solver.Alan Mishchenko2018-02-201-33/+81
* Improvements to circuit based solver.Alan Mishchenko2018-02-171-193/+490
* Extending MiniLUT to return attributes.Alan Mishchenko2018-02-111-0/+19
* Experiments with LUT mapping.Alan Mishchenko2018-02-102-9/+47
* Improvements to NDR to represent hierarchical designs.Alan Mishchenko2018-02-051-2/+2
* Improvements to NDR to represent hierarchical designs.Alan Mishchenko2018-02-051-1/+1
* Improvements to NDR to represent hierarchical designs.Alan Mishchenko2018-02-051-47/+198
* Adding support of reading and writing designs using a new internal format.Alan Mishchenko2018-01-281-1/+2
* Experiments with circuit-based SAT.Alan Mishchenko2018-01-271-26/+225
* Experiments with circuit-based SAT.Alan Mishchenko2018-01-271-132/+94
* Experiments with circuit-based SAT.Alan Mishchenko2018-01-271-31/+38
* Experiments with circuit-based SAT.Alan Mishchenko2018-01-271-130/+161
* Experiments with circuit-based SAT.Alan Mishchenko2018-01-274-0/+1293
* Experiments with SAT-based simulation.Alan Mishchenko2018-01-253-8/+42
* Experiments with SAT-based simulation.Alan Mishchenko2018-01-233-3/+122
* Fixed crash in &nf when there is no buffer gate.Alan Mishchenko2018-01-121-0/+5
* Corner-case bug fixed in CNF generation.Alan Mishchenko2017-12-281-0/+1
* Corner-case bug fixed in CNF generation.Alan Mishchenko2017-12-281-1/+6
* Experiments with AIG-based simulation.Alan Mishchenko2017-12-053-11/+244
* Adding switch -a to 'write_verilog' to write factored forms without XORs and ...Alan Mishchenko2017-12-032-11/+11
* Portability changes for gcc-6 suggested by Clifford.Alan Mishchenko2017-12-021-6/+4
* Improvements to AIG-based quantification.Alan Mishchenko2017-11-265-247/+548
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