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* Changes to enable CEX minimization.Alan Mishchenko2011-08-011-0/+1
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* Changes to enable CEX minimization.Alan Mishchenko2011-08-012-0/+332
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* Bug fix in &abs_cba.Alan Mishchenko2011-08-013-10/+122
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* Reducing print-out in 'bmc3'.Alan Mishchenko2011-08-011-9/+9
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* Undoing previous change in 'resim' (do not initialize flops using their ↵Alan Mishchenko2011-08-011-2/+12
| | | | values in the CEX because the number of flops in the CEX can be different).
* Minor bug fix in 'testcex' (made it consider outputs in direct order).Alan Mishchenko2011-08-011-1/+2
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* Added new APIs to the AIG manager.Alan Mishchenko2011-07-311-0/+1
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* Improvements to 'bmc3' (start frame; stop when all POs are SAT; stop when ↵Alan Mishchenko2011-07-311-3/+22
| | | | 2^nRegs frames are completed).
* Changes to enable smarter simulation.Alan Mishchenko2011-07-301-0/+8
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* Changes to enable smarter simulation.Alan Mishchenko2011-07-301-3/+5
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* Added generation of counter-examples to induction in 'ind'.Alan Mishchenko2011-07-303-7/+45
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* Changes to enable smarter simulation.Alan Mishchenko2011-07-303-840/+837
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* Changes to enable smarter simulation.Alan Mishchenko2011-07-303-59/+126
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* Changes to enable smarter simulation.Alan Mishchenko2011-07-303-24/+179
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* Improving and updating the abstraction code.Alan Mishchenko2011-07-296-78/+580
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* Added deriving abstraction in GIA from the precomputed flop map.Alan Mishchenko2011-07-296-60/+108
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* Improving and updating the abstraction code.Alan Mishchenko2011-07-2911-1625/+777
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* Changes to enable smarter simulation.Alan Mishchenko2011-07-296-85/+982
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* Adding procedures to find the care bits of a counter-example (update).Alan Mishchenko2011-07-274-56/+730
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* Added random generation of 64-bit numbers.Alan Mishchenko2011-07-272-3/+21
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* Adding procedures to find the care bits of a counter-example (update).Alan Mishchenko2011-07-252-2/+2
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* Adding procedures to find the care bits of a counter-example.Alan Mishchenko2011-07-253-0/+432
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* Bug fix in how seq cleanup handles cand equiv classes.Alan Mishchenko2011-07-251-1/+3
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* Added support for constraints in AIGER (bug fix).Alan Mishchenko2011-07-221-2/+7
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* Adding &equiv3, a new way of refining equivalence classes.Alan Mishchenko2011-07-222-13/+62
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* Added support for constraints in AIGER (bug fix).Alan Mishchenko2011-07-211-3/+3
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* Added support for constraints in AIGER (bug fix).Alan Mishchenko2011-07-211-6/+6
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* Changes to enable smarter simulation.Alan Mishchenko2011-07-214-29/+143
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* Added support for constraints in AIGER (bug fix).Alan Mishchenko2011-07-213-34/+72
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* Added support for constraints in AIGER (bug fix).Alan Mishchenko2011-07-201-3/+3
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* Changes to enable smarter simulation.Alan Mishchenko2011-07-204-0/+434
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* New demitering features.Alan Mishchenko2011-07-202-0/+95
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* Added support for constraints in AIGER (bug fix).Alan Mishchenko2011-07-201-0/+5
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* Added support for constraints in AIGER.Alan Mishchenko2011-07-202-11/+97
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* Added report about exceeding the conflict limit in 'ind'.Alan Mishchenko2011-07-191-1/+3
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* Diagnostic printout for random simulationAlan Mishchenko2011-07-161-0/+118
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* Fixed a glitch in &dch, which removed the flops.Alan Mishchenko2011-07-161-0/+1
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* Fixed memory leak in the AIGER reader.Alan Mishchenko2011-07-131-0/+1
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* Added equivalence class computation for flop outputs only in &equiv2.Alan Mishchenko2011-07-131-4/+4
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* Added a new demitering feature for dual-output miters.Alan Mishchenko2011-07-024-0/+80
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* Fixed the problem in mapping with the new check.Alan Mishchenko2011-06-263-3/+3
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* Added command &filter to filter equiv classes.Alan Mishchenko2011-06-152-137/+391
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* Adding command 'srm2' (additional feature).Alan Mishchenko2011-06-081-1/+9
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* Adding command 'srm2'.Alan Mishchenko2011-06-082-2/+134
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* Added new command 'outdec'.Alan Mishchenko2011-05-193-0/+208
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* Added conversion of cex after phase abstraction.Alan Mishchenko2011-05-181-0/+43
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* Fixing mismatch in reconcile.Alan Mishchenko2011-05-131-1/+11
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* Improvements to timeout.Alan Mishchenko2011-05-111-10/+13
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* Improvements in sequential verification.Alan Mishchenko2011-05-071-5/+164
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* Improvements in sequential verification.Alan Mishchenko2011-05-071-9/+4
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