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yosys-experimental
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aig
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Age
Files
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*
Compiler warning.
Alan Mishchenko
2019-01-30
1
-1
/
+1
|
*
Exploring other ways of CEX writing.
Alan Mishchenko
2019-01-21
5
-6
/
+9
|
*
Experiment with partitioned &scorr.
Alan Mishchenko
2019-01-15
1
-0
/
+185
|
*
Adding one API of GIA manager.
Alan Mishchenko
2019-01-12
1
-0
/
+18
|
*
Bug fix in deriving names for the miter output.
Alan Mishchenko
2019-01-10
1
-4
/
+9
|
*
Fixing float overflow during area-flow computation in &lf.
Alan Mishchenko
2018-12-13
1
-0
/
+8
|
*
Experiments with retiming (adding new APIs).
Alan Mishchenko
2018-12-09
1
-0
/
+2
|
*
Adding switch &w -n to modify the comment section of the AIGER file written.
Alan Mishchenko
2018-11-21
10
-17
/
+16
|
*
Adding an option to write new-line after the comment symbol when dumping an ↵
Alan Mishchenko
2018-11-20
1
-2
/
+7
|
|
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AIGER file.
*
Undoing some of the previous changes.
Alan Mishchenko
2018-11-15
1
-1
/
+5
|
*
Procedures to verify equivalence classes.
Alan Mishchenko
2018-11-11
1
-1
/
+139
|
*
Several recent bug fixes.
Alan Mishchenko
2018-11-04
2
-4
/
+3
|
*
Fix timing info communication in GIA APIs.
Alan Mishchenko
2018-10-23
1
-0
/
+1
|
*
Fix timing info communication in GIA APIs.
Alan Mishchenko
2018-10-23
1
-0
/
+1
|
*
Fix timing info communication in GIA APIs.
Alan Mishchenko
2018-10-22
2
-1
/
+27
|
*
Experiments with word-level retiming.
Alan Mishchenko
2018-09-30
1
-2
/
+5
|
*
Preserving output names while deriving a miter.
Alan Mishchenko
2018-09-20
1
-0
/
+26
|
*
Preserving names while deriving a miter.
Alan Mishchenko
2018-09-20
1
-0
/
+2
|
*
Procedure to return seq equivalences.
Alan Mishchenko
2018-07-22
1
-0
/
+68
|
*
Extending NDR to support adder/subtractor.
Alan Mishchenko
2018-06-14
1
-0
/
+36
|
*
Bug fix (accessing unassigned memory).
Alan Mishchenko
2018-06-12
1
-1
/
+7
|
*
Compiler warnings.
Alan Mishchenko
2018-06-08
2
-3
/
+4
|
*
Supporting the decoder primitive in NDR and bit-blasting.
Alan Mishchenko
2018-06-05
2
-1
/
+33
|
*
Disabling unused feature in &nf.
Alan Mishchenko
2018-06-04
1
-0
/
+2
|
*
Supporting NMUX and SEL in NDR.
Alan Mishchenko
2018-05-24
1
-0
/
+55
|
*
Updates to NDR format (bug fixes).
Alan Mishchenko
2018-05-03
2
-21
/
+29
|
*
Updates to NDR format (flops, memories, signed mult, etc).
Alan Mishchenko
2018-04-29
2
-61
/
+244
|
*
Adding switch &w -p to dump AIG in a Verilog file.
Alan Mishchenko
2018-04-25
2
-0
/
+186
|
*
Adding adder-subtractor primitive.
Alan Mishchenko
2018-04-11
1
-1
/
+3
|
*
Making sure duplicated inverters are not created.
Alan Mishchenko
2018-04-11
1
-3
/
+9
|
*
Integrating SAT-based CEX minimization (bug fix).
Alan Mishchenko
2018-03-25
1
-4
/
+8
|
*
Integrating SAT-based CEX minimization.
Alan Mishchenko
2018-03-25
1
-2
/
+106
|
*
Updating &mfs to support hard objects.
Alan Mishchenko
2018-03-23
1
-2
/
+25
|
*
Adding switch 'scorr -f' to dump inductive invariant as an AIG.
Alan Mishchenko
2018-03-22
2
-2
/
+4
|
*
Adding parameters and improvements to %blast.
Alan Mishchenko
2018-02-28
1
-3
/
+3
|
*
Adding support for adders with carry-in in WLC and NDR.
Alan Mishchenko
2018-02-24
1
-0
/
+98
|
*
Improvements to circuit based solver.
Alan Mishchenko
2018-02-20
1
-33
/
+81
|
*
Improvements to circuit based solver.
Alan Mishchenko
2018-02-17
1
-193
/
+490
|
*
Extending MiniLUT to return attributes.
Alan Mishchenko
2018-02-11
1
-0
/
+19
|
*
Experiments with LUT mapping.
Alan Mishchenko
2018-02-10
2
-9
/
+47
|
*
Improvements to NDR to represent hierarchical designs.
Alan Mishchenko
2018-02-05
1
-2
/
+2
|
*
Improvements to NDR to represent hierarchical designs.
Alan Mishchenko
2018-02-05
1
-1
/
+1
|
*
Improvements to NDR to represent hierarchical designs.
Alan Mishchenko
2018-02-05
1
-47
/
+198
|
*
Adding support of reading and writing designs using a new internal format.
Alan Mishchenko
2018-01-28
1
-1
/
+2
|
*
Experiments with circuit-based SAT.
Alan Mishchenko
2018-01-27
1
-26
/
+225
|
*
Experiments with circuit-based SAT.
Alan Mishchenko
2018-01-27
1
-132
/
+94
|
*
Experiments with circuit-based SAT.
Alan Mishchenko
2018-01-27
1
-31
/
+38
|
*
Experiments with circuit-based SAT.
Alan Mishchenko
2018-01-27
1
-130
/
+161
|
*
Experiments with circuit-based SAT.
Alan Mishchenko
2018-01-27
4
-0
/
+1293
|
*
Experiments with SAT-based simulation.
Alan Mishchenko
2018-01-25
3
-8
/
+42
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