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* Supporting the decoder primitive in NDR and bit-blasting.Alan Mishchenko2018-06-052-1/+33
* Disabling unused feature in &nf.Alan Mishchenko2018-06-041-0/+2
* Supporting NMUX and SEL in NDR.Alan Mishchenko2018-05-241-0/+55
* Updates to NDR format (bug fixes).Alan Mishchenko2018-05-032-21/+29
* Updates to NDR format (flops, memories, signed mult, etc).Alan Mishchenko2018-04-292-61/+244
* Adding switch &w -p to dump AIG in a Verilog file.Alan Mishchenko2018-04-252-0/+186
* Adding adder-subtractor primitive.Alan Mishchenko2018-04-111-1/+3
* Making sure duplicated inverters are not created.Alan Mishchenko2018-04-111-3/+9
* Integrating SAT-based CEX minimization (bug fix).Alan Mishchenko2018-03-251-4/+8
* Integrating SAT-based CEX minimization.Alan Mishchenko2018-03-251-2/+106
* Updating &mfs to support hard objects.Alan Mishchenko2018-03-231-2/+25
* Adding switch 'scorr -f' to dump inductive invariant as an AIG.Alan Mishchenko2018-03-222-2/+4
* Adding parameters and improvements to %blast.Alan Mishchenko2018-02-281-3/+3
* Adding support for adders with carry-in in WLC and NDR.Alan Mishchenko2018-02-241-0/+98
* Improvements to circuit based solver.Alan Mishchenko2018-02-201-33/+81
* Improvements to circuit based solver.Alan Mishchenko2018-02-171-193/+490
* Extending MiniLUT to return attributes.Alan Mishchenko2018-02-111-0/+19
* Experiments with LUT mapping.Alan Mishchenko2018-02-102-9/+47
* Improvements to NDR to represent hierarchical designs.Alan Mishchenko2018-02-051-2/+2
* Improvements to NDR to represent hierarchical designs.Alan Mishchenko2018-02-051-1/+1
* Improvements to NDR to represent hierarchical designs.Alan Mishchenko2018-02-051-47/+198
* Adding support of reading and writing designs using a new internal format.Alan Mishchenko2018-01-281-1/+2
* Experiments with circuit-based SAT.Alan Mishchenko2018-01-271-26/+225
* Experiments with circuit-based SAT.Alan Mishchenko2018-01-271-132/+94
* Experiments with circuit-based SAT.Alan Mishchenko2018-01-271-31/+38
* Experiments with circuit-based SAT.Alan Mishchenko2018-01-271-130/+161
* Experiments with circuit-based SAT.Alan Mishchenko2018-01-274-0/+1293
* Experiments with SAT-based simulation.Alan Mishchenko2018-01-253-8/+42
* Experiments with SAT-based simulation.Alan Mishchenko2018-01-233-3/+122
* Fixed crash in &nf when there is no buffer gate.Alan Mishchenko2018-01-121-0/+5
* Corner-case bug fixed in CNF generation.Alan Mishchenko2017-12-281-0/+1
* Corner-case bug fixed in CNF generation.Alan Mishchenko2017-12-281-1/+6
* Experiments with AIG-based simulation.Alan Mishchenko2017-12-053-11/+244
* Adding switch -a to 'write_verilog' to write factored forms without XORs and ...Alan Mishchenko2017-12-032-11/+11
* Portability changes for gcc-6 suggested by Clifford.Alan Mishchenko2017-12-021-6/+4
* Improvements to AIG-based quantification.Alan Mishchenko2017-11-265-247/+548
* C++ compatibility: fix incompatible parameter listBaruch Sterin2017-11-231-1/+1
* C++ compatibility: cast returned void*Baruch Sterin2017-11-231-2/+2
* Experimental CEX minimization code.Alan Mishchenko2017-11-231-0/+116
* Extracting CSAT interface and several cleanups.Alan Mishchenko2017-11-134-10/+26
* Changes to make GIA structural hashing use a dedicated array instead of pObj-...Alan Mishchenko2017-11-135-71/+75
* Improvements to quantification.Alan Mishchenko2017-11-133-0/+251
* Profiling quantification and other changes.Alan Mishchenko2017-11-062-0/+6
* Profiling quantification and other changes.Alan Mishchenko2017-11-064-1/+212
* Improvements to quantification.Alan Mishchenko2017-10-292-0/+80
* Small fix. Garanteeing pPars is not NULL before checking pPars->fSlacksBruno Schmitt2017-10-241-1/+1
* Adding API to dump MiniAIG into a Verilog file and other small changes.Alan Mishchenko2017-10-223-7/+127
* Integrating Glucose into &qbf.Alan Mishchenko2017-10-171-3/+3
* Integrating Glucose into &qbf.Alan Mishchenko2017-10-171-9/+32
* Improvements to SAT based SOP computation.Alan Mishchenko2017-10-062-0/+8
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