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Age
Files
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...
*
Supporting the decoder primitive in NDR and bit-blasting.
Alan Mishchenko
2018-06-05
2
-1
/
+33
*
Disabling unused feature in &nf.
Alan Mishchenko
2018-06-04
1
-0
/
+2
*
Supporting NMUX and SEL in NDR.
Alan Mishchenko
2018-05-24
1
-0
/
+55
*
Updates to NDR format (bug fixes).
Alan Mishchenko
2018-05-03
2
-21
/
+29
*
Updates to NDR format (flops, memories, signed mult, etc).
Alan Mishchenko
2018-04-29
2
-61
/
+244
*
Adding switch &w -p to dump AIG in a Verilog file.
Alan Mishchenko
2018-04-25
2
-0
/
+186
*
Adding adder-subtractor primitive.
Alan Mishchenko
2018-04-11
1
-1
/
+3
*
Making sure duplicated inverters are not created.
Alan Mishchenko
2018-04-11
1
-3
/
+9
*
Integrating SAT-based CEX minimization (bug fix).
Alan Mishchenko
2018-03-25
1
-4
/
+8
*
Integrating SAT-based CEX minimization.
Alan Mishchenko
2018-03-25
1
-2
/
+106
*
Updating &mfs to support hard objects.
Alan Mishchenko
2018-03-23
1
-2
/
+25
*
Adding switch 'scorr -f' to dump inductive invariant as an AIG.
Alan Mishchenko
2018-03-22
2
-2
/
+4
*
Adding parameters and improvements to %blast.
Alan Mishchenko
2018-02-28
1
-3
/
+3
*
Adding support for adders with carry-in in WLC and NDR.
Alan Mishchenko
2018-02-24
1
-0
/
+98
*
Improvements to circuit based solver.
Alan Mishchenko
2018-02-20
1
-33
/
+81
*
Improvements to circuit based solver.
Alan Mishchenko
2018-02-17
1
-193
/
+490
*
Extending MiniLUT to return attributes.
Alan Mishchenko
2018-02-11
1
-0
/
+19
*
Experiments with LUT mapping.
Alan Mishchenko
2018-02-10
2
-9
/
+47
*
Improvements to NDR to represent hierarchical designs.
Alan Mishchenko
2018-02-05
1
-2
/
+2
*
Improvements to NDR to represent hierarchical designs.
Alan Mishchenko
2018-02-05
1
-1
/
+1
*
Improvements to NDR to represent hierarchical designs.
Alan Mishchenko
2018-02-05
1
-47
/
+198
*
Adding support of reading and writing designs using a new internal format.
Alan Mishchenko
2018-01-28
1
-1
/
+2
*
Experiments with circuit-based SAT.
Alan Mishchenko
2018-01-27
1
-26
/
+225
*
Experiments with circuit-based SAT.
Alan Mishchenko
2018-01-27
1
-132
/
+94
*
Experiments with circuit-based SAT.
Alan Mishchenko
2018-01-27
1
-31
/
+38
*
Experiments with circuit-based SAT.
Alan Mishchenko
2018-01-27
1
-130
/
+161
*
Experiments with circuit-based SAT.
Alan Mishchenko
2018-01-27
4
-0
/
+1293
*
Experiments with SAT-based simulation.
Alan Mishchenko
2018-01-25
3
-8
/
+42
*
Experiments with SAT-based simulation.
Alan Mishchenko
2018-01-23
3
-3
/
+122
*
Fixed crash in &nf when there is no buffer gate.
Alan Mishchenko
2018-01-12
1
-0
/
+5
*
Corner-case bug fixed in CNF generation.
Alan Mishchenko
2017-12-28
1
-0
/
+1
*
Corner-case bug fixed in CNF generation.
Alan Mishchenko
2017-12-28
1
-1
/
+6
*
Experiments with AIG-based simulation.
Alan Mishchenko
2017-12-05
3
-11
/
+244
*
Adding switch -a to 'write_verilog' to write factored forms without XORs and ...
Alan Mishchenko
2017-12-03
2
-11
/
+11
*
Portability changes for gcc-6 suggested by Clifford.
Alan Mishchenko
2017-12-02
1
-6
/
+4
*
Improvements to AIG-based quantification.
Alan Mishchenko
2017-11-26
5
-247
/
+548
*
C++ compatibility: fix incompatible parameter list
Baruch Sterin
2017-11-23
1
-1
/
+1
*
C++ compatibility: cast returned void*
Baruch Sterin
2017-11-23
1
-2
/
+2
*
Experimental CEX minimization code.
Alan Mishchenko
2017-11-23
1
-0
/
+116
*
Extracting CSAT interface and several cleanups.
Alan Mishchenko
2017-11-13
4
-10
/
+26
*
Changes to make GIA structural hashing use a dedicated array instead of pObj-...
Alan Mishchenko
2017-11-13
5
-71
/
+75
*
Improvements to quantification.
Alan Mishchenko
2017-11-13
3
-0
/
+251
*
Profiling quantification and other changes.
Alan Mishchenko
2017-11-06
2
-0
/
+6
*
Profiling quantification and other changes.
Alan Mishchenko
2017-11-06
4
-1
/
+212
*
Improvements to quantification.
Alan Mishchenko
2017-10-29
2
-0
/
+80
*
Small fix. Garanteeing pPars is not NULL before checking pPars->fSlacks
Bruno Schmitt
2017-10-24
1
-1
/
+1
*
Adding API to dump MiniAIG into a Verilog file and other small changes.
Alan Mishchenko
2017-10-22
3
-7
/
+127
*
Integrating Glucose into &qbf.
Alan Mishchenko
2017-10-17
1
-3
/
+3
*
Integrating Glucose into &qbf.
Alan Mishchenko
2017-10-17
1
-9
/
+32
*
Improvements to SAT based SOP computation.
Alan Mishchenko
2017-10-06
2
-0
/
+8
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