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* Updates to NDR format (bug fixes).Alan Mishchenko2018-05-032-21/+29
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* Updates to NDR format (flops, memories, signed mult, etc).Alan Mishchenko2018-04-292-61/+244
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* Adding switch &w -p to dump AIG in a Verilog file.Alan Mishchenko2018-04-252-0/+186
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* Adding adder-subtractor primitive.Alan Mishchenko2018-04-111-1/+3
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* Making sure duplicated inverters are not created.Alan Mishchenko2018-04-111-3/+9
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* Integrating SAT-based CEX minimization (bug fix).Alan Mishchenko2018-03-251-4/+8
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* Integrating SAT-based CEX minimization.Alan Mishchenko2018-03-251-2/+106
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* Updating &mfs to support hard objects.Alan Mishchenko2018-03-231-2/+25
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* Adding switch 'scorr -f' to dump inductive invariant as an AIG.Alan Mishchenko2018-03-222-2/+4
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* Adding parameters and improvements to %blast.Alan Mishchenko2018-02-281-3/+3
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* Adding support for adders with carry-in in WLC and NDR.Alan Mishchenko2018-02-241-0/+98
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* Improvements to circuit based solver.Alan Mishchenko2018-02-201-33/+81
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* Improvements to circuit based solver.Alan Mishchenko2018-02-171-193/+490
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* Extending MiniLUT to return attributes.Alan Mishchenko2018-02-111-0/+19
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* Experiments with LUT mapping.Alan Mishchenko2018-02-102-9/+47
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* Improvements to NDR to represent hierarchical designs.Alan Mishchenko2018-02-051-2/+2
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* Improvements to NDR to represent hierarchical designs.Alan Mishchenko2018-02-051-1/+1
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* Improvements to NDR to represent hierarchical designs.Alan Mishchenko2018-02-051-47/+198
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* Adding support of reading and writing designs using a new internal format.Alan Mishchenko2018-01-281-1/+2
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* Experiments with circuit-based SAT.Alan Mishchenko2018-01-271-26/+225
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* Experiments with circuit-based SAT.Alan Mishchenko2018-01-271-132/+94
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* Experiments with circuit-based SAT.Alan Mishchenko2018-01-271-31/+38
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* Experiments with circuit-based SAT.Alan Mishchenko2018-01-271-130/+161
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* Experiments with circuit-based SAT.Alan Mishchenko2018-01-274-0/+1293
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* Experiments with SAT-based simulation.Alan Mishchenko2018-01-253-8/+42
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* Experiments with SAT-based simulation.Alan Mishchenko2018-01-233-3/+122
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* Fixed crash in &nf when there is no buffer gate.Alan Mishchenko2018-01-121-0/+5
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* Corner-case bug fixed in CNF generation.Alan Mishchenko2017-12-281-0/+1
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* Corner-case bug fixed in CNF generation.Alan Mishchenko2017-12-281-1/+6
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* Experiments with AIG-based simulation.Alan Mishchenko2017-12-053-11/+244
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* Adding switch -a to 'write_verilog' to write factored forms without XORs and ↵Alan Mishchenko2017-12-032-11/+11
| | | | MUXes.
* Portability changes for gcc-6 suggested by Clifford.Alan Mishchenko2017-12-021-6/+4
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* Improvements to AIG-based quantification.Alan Mishchenko2017-11-265-247/+548
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* C++ compatibility: fix incompatible parameter listBaruch Sterin2017-11-231-1/+1
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* C++ compatibility: cast returned void*Baruch Sterin2017-11-231-2/+2
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* Experimental CEX minimization code.Alan Mishchenko2017-11-231-0/+116
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* Extracting CSAT interface and several cleanups.Alan Mishchenko2017-11-134-10/+26
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* Changes to make GIA structural hashing use a dedicated array instead of ↵Alan Mishchenko2017-11-135-71/+75
| | | | pObj->Value.
* Improvements to quantification.Alan Mishchenko2017-11-133-0/+251
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* Profiling quantification and other changes.Alan Mishchenko2017-11-062-0/+6
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* Profiling quantification and other changes.Alan Mishchenko2017-11-064-1/+212
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* Improvements to quantification.Alan Mishchenko2017-10-292-0/+80
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* Small fix. Garanteeing pPars is not NULL before checking pPars->fSlacksBruno Schmitt2017-10-241-1/+1
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* Adding API to dump MiniAIG into a Verilog file and other small changes.Alan Mishchenko2017-10-223-7/+127
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* Integrating Glucose into &qbf.Alan Mishchenko2017-10-171-3/+3
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* Integrating Glucose into &qbf.Alan Mishchenko2017-10-171-9/+32
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* Improvements to SAT based SOP computation.Alan Mishchenko2017-10-062-0/+8
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* Updates and bug fixes.Alan Mishchenko2017-10-041-1/+1
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* Adding printout of slack distribution for mapped networks.Alan Mishchenko2017-10-022-0/+321
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* Maintenance and updates.Alan Mishchenko2017-09-242-4/+10
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