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iCE40/abc
yosys-experimental
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abc.c
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Author
Age
Files
Lines
*
Expriments with functions.
Alan Mishchenko
2018-09-08
1
-5
/
+21
*
Expriments with functions.
Alan Mishchenko
2018-09-08
1
-7
/
+7
*
Expriments with functions (bug fixes).
Alan Mishchenko
2018-09-07
1
-0
/
+11
*
Expriments with functions.
Alan Mishchenko
2018-09-07
1
-0
/
+67
*
Expriments with functions (compiler warnings).
Alan Mishchenko
2018-08-30
1
-0
/
+1
*
Expriments with functions.
Alan Mishchenko
2018-08-29
1
-0
/
+1
*
Complication problem fix.
Alan Mishchenko
2018-08-19
1
-1
/
+0
*
Experiments with function enumeration.
Alan Mishchenko
2018-08-01
1
-0
/
+1
*
Updating command 'majgen'.
Alan Mishchenko
2018-07-04
1
-5
/
+9
*
Bug fix.
Alan Mishchenko
2018-07-04
1
-1
/
+0
*
Generating adder-trees using 'gen -b -A <num> -N <num> <file>.v'.
Alan Mishchenko
2018-07-04
1
-2
/
+32
*
Adding command 'majgen'.
Alan Mishchenko
2018-07-04
1
-0
/
+54
*
Enabling user-specified output signature in &polyn.
Alan Mishchenko
2018-06-13
1
-6
/
+32
*
Experiments with path enumeration.
Alan Mishchenko
2018-06-10
1
-2
/
+60
*
Adding switch 'clp -o' to reverse initial variable ordering.
Alan Mishchenko
2018-06-07
1
-8
/
+14
*
Experiments with path enumeration.
Alan Mishchenko
2018-06-06
1
-1
/
+1
*
Adding command print_mint.
Alan Mishchenko
2018-06-04
1
-0
/
+64
*
Simple BDD package.
Alan Mishchenko
2018-05-23
1
-1
/
+3
*
Bug fix in &sat -x.
Alan Mishchenko
2018-05-07
1
-2
/
+3
*
Adding &sat -x to save CEXes for multi-output combinational miters.
Alan Mishchenko
2018-05-06
1
-4
/
+33
*
Adding switch &w -p to dump AIG in a Verilog file.
Alan Mishchenko
2018-04-25
1
-2
/
+9
*
The ECO code.
Alan Mishchenko
2018-04-25
1
-2
/
+11
*
The ECO code.
Alan Mishchenko
2018-04-25
1
-6
/
+6
*
Typo in the command description.
Alan Mishchenko
2018-04-25
1
-5
/
+5
*
Memory abstraction.
Alan Mishchenko
2018-04-15
1
-0
/
+2
*
Adding new NPN code developed by XueGong Zhou at Fudan University.
Alan Mishchenko
2018-03-25
1
-0
/
+1
*
Adding switch 'scorr -f' to dump inductive invariant as an AIG.
Alan Mishchenko
2018-03-22
1
-5
/
+14
*
Experiments with LUT mapping.
Alan Mishchenko
2018-02-10
1
-5
/
+18
*
Improvements to NDR to represent hierarchical designs.
Alan Mishchenko
2018-02-05
1
-2
/
+1
*
Improvements to NDR to represent hierarchical designs.
Alan Mishchenko
2018-02-05
1
-1
/
+2
*
Experiments with circuit-based SAT.
Alan Mishchenko
2018-01-27
1
-4
/
+15
*
Experiments with SAT-based simulation.
Alan Mishchenko
2018-01-25
1
-1
/
+1
*
Updates to exact synthesis commands.
Alan Mishchenko
2018-01-19
1
-4
/
+26
*
New command 'testexact'.
Alan Mishchenko
2018-01-04
1
-0
/
+51
*
New exact synthesis command 'allexact'.
Alan Mishchenko
2017-12-30
1
-2
/
+2
*
New exact synthesis command 'allexact'.
Alan Mishchenko
2017-12-28
1
-1
/
+170
*
Adding parameter structure to 'twoexact' and 'lutexact'.
Alan Mishchenko
2017-12-06
1
-59
/
+71
*
An improvement to 'twoexact' and 'lutexact'.
Alan Mishchenko
2017-12-06
1
-0
/
+27
*
An improvement to 'twoexact' and 'lutexact'.
Alan Mishchenko
2017-12-06
1
-2
/
+2
*
Switch -a to use only AND-gates in 'twoexact' and 'lutexact'.
Alan Mishchenko
2017-12-06
1
-14
/
+22
*
New command 'lutexact'.
Alan Mishchenko
2017-12-05
1
-0
/
+104
*
Adding switch -a to 'write_verilog' to write factored forms without XORs and ...
Alan Mishchenko
2017-12-03
1
-1
/
+1
*
Adding API to dump MiniAIG into a Verilog file and other small changes.
Alan Mishchenko
2017-10-22
1
-1
/
+1
*
Adding random search in exact synthesis.
Alan Mishchenko
2017-10-20
1
-6
/
+23
*
Integrating old SAT solver into majexact and twoexact.
Alan Mishchenko
2017-10-19
1
-11
/
+27
*
Integrating Glucose into &qbf.
Alan Mishchenko
2017-10-17
1
-6
/
+11
*
Fix the build.
Alan Mishchenko
2017-10-11
1
-1
/
+0
*
Another variation on exact synthesis.
Alan Mishchenko
2017-10-11
1
-1
/
+80
*
Adding printout of slack distribution for mapped networks.
Alan Mishchenko
2017-10-02
1
-3
/
+7
*
Exact synthesis of majority gates.
Alan Mishchenko
2017-10-01
1
-14
/
+18
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