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path: root/src/base/abci/abcDar.c
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* Fix mismatch in output formatting.Alan Mishchenko2017-01-211-6/+6
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* Changes for delay-oriented computation.Alan Mishchenko2015-10-231-1/+1
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* More tuning in &nf.Alan Mishchenko2015-08-281-1/+1
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* Changes to be able to compile ABC without CUDD.Alan Mishchenko2015-08-241-1/+1
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* Changes to be able to compile ABC without CUDD.Alan Mishchenko2015-08-241-1/+1
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* Correcting assert in converting standard cell mapping from GIA into ABC.Alan Mishchenko2015-04-271-1/+1
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* Trying to reduce delay degradation afer 'map' with user timing.Alan Mishchenko2015-03-241-0/+1
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* Improvements and tuning of CBA.Alan Mishchenko2015-02-011-1/+1
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* Organizing commands for barbuf-aware flow.Alan Mishchenko2015-01-201-8/+13
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* Integrating barrier buffers.Alan Mishchenko2014-12-111-4/+3
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* Converting AIG with MUXes into a logic network.Alan Mishchenko2014-12-101-15/+52
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* Integrating barrier buffers.Alan Mishchenko2014-12-081-5/+65
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* Added switches '-c' and '-n' to 'init'.Alan Mishchenko2014-11-021-1/+1
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* Small changes.Alan Mishchenko2014-07-291-1/+1
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* Adding support for standard-cell mapping.Alan Mishchenko2014-07-281-0/+111
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* Improvements to CNF generation.Alan Mishchenko2014-06-231-2/+2
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* merge unfold2Jiang Long2014-06-041-1/+1
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* Pass file name correctly.Alan Mishchenko2014-04-101-3/+4
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* Mismatch in bmc3 printout.Alan Mishchenko2014-03-301-2/+2
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* Updating code to support barrier buffers.Alan Mishchenko2014-03-181-0/+7
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* Adding barrier buffers.Alan Mishchenko2014-03-161-0/+5
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* Multi-output property solver.Alan Mishchenko2013-10-261-3/+4
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* Multi-output property solver.Alan Mishchenko2013-10-231-38/+44
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* Adding switch &get -m to import mapped network into the &-space.Alan Mishchenko2013-09-011-1/+1
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* Adding timeout to command 'ind'.Alan Mishchenko2013-06-281-2/+2
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* Unifying representation of mapping in GIA.Alan Mishchenko2013-06-251-1/+1
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* Adding a wrapper around clock() for more accurate time counting in ABC.Alan Mishchenko2013-05-271-58/+58
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* Adding runtime limit per output to multi-output DPR (pdr -H <num_sec>).Alan Mishchenko2013-05-031-15/+28
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* Adding parameter structure for rarity simulation.Alan Mishchenko2013-04-171-2/+2
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* Updating 'sim3' to move the design into the last rare state.Alan Mishchenko2013-04-011-2/+3
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* Added dumping QDIMACS files in command 'qbf'.Alan Mishchenko2013-03-271-1/+1
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* Adding new features to 'dualrail'.Alan Mishchenko2013-02-211-0/+3
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* Adding new features to 'dualrail'.Alan Mishchenko2013-02-211-0/+23
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* Added 'gap timeout' to bmc3 and sim3.Alan Mishchenko2013-02-151-2/+2
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* Enabled detecting CEXes in multiple POs without stopping (sim3 -a).Alan Mishchenko2013-01-231-2/+5
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* Enabled detecting CEXes in multiple POs without stopping (sim3 -a).Alan Mishchenko2013-01-231-2/+2
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* Fixing C++ compilation issues.Alan Mishchenko2013-01-081-1/+1
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* Enabling multi-output solving in 'pdr'.Alan Mishchenko2012-12-091-2/+2
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* Enabling multi-output solving in 'pdr'.Alan Mishchenko2012-12-091-4/+4
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* Enabling multi-output solving in 'pdr'.Alan Mishchenko2012-12-091-15/+29
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* Enabling multi-output solving in 'pdr'.Alan Mishchenko2012-12-091-29/+18
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* Enabling multi-output solving in 'pdr'.Alan Mishchenko2012-12-091-1/+9
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* Enabling multi-output solving in 'pdr'.Alan Mishchenko2012-12-091-1/+5
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* Isolating BMC code into a separate package.Alan Mishchenko2012-11-141-0/+1
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* Performance bug fix in choice generation.Alan Mishchenko2012-11-091-11/+18
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* Integrating GIA with LUT mapping.Alan Mishchenko2012-10-241-0/+144
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* Extending BLIF parser/write to hangle multi-output cells.Alan Mishchenko2012-09-191-2/+2
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* Prepared &gla to try abstracting and proving concurrently.Alan Mishchenko2012-09-141-1/+1
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* Prepared &gla to try abstracting and proving concurrently.Alan Mishchenko2012-09-141-9/+12
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* Unified print-out of property failures produced by all engines.Alan Mishchenko2012-09-091-5/+5
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