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path: root/src/base/abci/abcDar.c
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* Adding switch to stop scorr if refinement is too slow.Alan Mishchenko2022-04-241-1/+2
* Experiments with word-level data structures.Alan Mishchenko2022-04-041-0/+27
* Disabling choices when they are computed incorrectly.Alan Mishchenko2021-11-301-1/+5
* Changing declaration of Vec_Ptr_t sorting function to satisfy some compilers.Alan Mishchenko2021-09-261-1/+1
* Upgrading choice computation.Alan Mishchenko2021-07-311-15/+21
* Disabled special handling of 2-input LUTs.Alan Mishchenko2021-06-031-1/+1
* Passing node labels.Alan Mishchenko2021-04-261-0/+1
* Adding switch -o to 'map' and '&put' to control gate duplication.Alan Mishchenko2019-10-261-6/+5
* Making 'dsec' return correct return value (undoing this change, made by mista...Alan Mishchenko2019-06-261-1/+1
* Making 'dsec' return correct return value.Alan Mishchenko2019-06-241-1/+1
* Making 'dsec' return verification status.Alan Mishchenko2019-06-211-1/+1
* Adding clock enable extraction as command &put -e.Alan Mishchenko2019-04-141-4/+66
* Compiler warning.Alan Mishchenko2019-03-281-1/+0
* Changing print-out in 'dprove' when the miter is combinational.Alan Mishchenko2019-03-271-10/+13
* Several changes to various packages.Alan Mishchenko2017-09-041-0/+29
* Integrating Satoko into 'bmc' and 'bmc2'.Alan Mishchenko2017-08-161-4/+4
* Fix mismatch in output formatting.Alan Mishchenko2017-01-211-6/+6
* Changes for delay-oriented computation.Alan Mishchenko2015-10-231-1/+1
* More tuning in &nf.Alan Mishchenko2015-08-281-1/+1
* Changes to be able to compile ABC without CUDD.Alan Mishchenko2015-08-241-1/+1
* Changes to be able to compile ABC without CUDD.Alan Mishchenko2015-08-241-1/+1
* Correcting assert in converting standard cell mapping from GIA into ABC.Alan Mishchenko2015-04-271-1/+1
* Trying to reduce delay degradation afer 'map' with user timing.Alan Mishchenko2015-03-241-0/+1
* Improvements and tuning of CBA.Alan Mishchenko2015-02-011-1/+1
* Organizing commands for barbuf-aware flow.Alan Mishchenko2015-01-201-8/+13
* Integrating barrier buffers.Alan Mishchenko2014-12-111-4/+3
* Converting AIG with MUXes into a logic network.Alan Mishchenko2014-12-101-15/+52
* Integrating barrier buffers.Alan Mishchenko2014-12-081-5/+65
* Added switches '-c' and '-n' to 'init'.Alan Mishchenko2014-11-021-1/+1
* Small changes.Alan Mishchenko2014-07-291-1/+1
* Adding support for standard-cell mapping.Alan Mishchenko2014-07-281-0/+111
* Improvements to CNF generation.Alan Mishchenko2014-06-231-2/+2
* merge unfold2Jiang Long2014-06-041-1/+1
* Pass file name correctly.Alan Mishchenko2014-04-101-3/+4
* Mismatch in bmc3 printout.Alan Mishchenko2014-03-301-2/+2
* Updating code to support barrier buffers.Alan Mishchenko2014-03-181-0/+7
* Adding barrier buffers.Alan Mishchenko2014-03-161-0/+5
* Multi-output property solver.Alan Mishchenko2013-10-261-3/+4
* Multi-output property solver.Alan Mishchenko2013-10-231-38/+44
* Adding switch &get -m to import mapped network into the &-space.Alan Mishchenko2013-09-011-1/+1
* Adding timeout to command 'ind'.Alan Mishchenko2013-06-281-2/+2
* Unifying representation of mapping in GIA.Alan Mishchenko2013-06-251-1/+1
* Adding a wrapper around clock() for more accurate time counting in ABC.Alan Mishchenko2013-05-271-58/+58
* Adding runtime limit per output to multi-output DPR (pdr -H <num_sec>).Alan Mishchenko2013-05-031-15/+28
* Adding parameter structure for rarity simulation.Alan Mishchenko2013-04-171-2/+2
* Updating 'sim3' to move the design into the last rare state.Alan Mishchenko2013-04-011-2/+3
* Added dumping QDIMACS files in command 'qbf'.Alan Mishchenko2013-03-271-1/+1
* Adding new features to 'dualrail'.Alan Mishchenko2013-02-211-0/+3
* Adding new features to 'dualrail'.Alan Mishchenko2013-02-211-0/+23
* Added 'gap timeout' to bmc3 and sim3.Alan Mishchenko2013-02-151-2/+2
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