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abci
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abcDar.c
Commit message (
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Author
Age
Files
Lines
*
Improvements and tuning of CBA.
Alan Mishchenko
2015-02-01
1
-1
/
+1
*
Organizing commands for barbuf-aware flow.
Alan Mishchenko
2015-01-20
1
-8
/
+13
*
Integrating barrier buffers.
Alan Mishchenko
2014-12-11
1
-4
/
+3
*
Converting AIG with MUXes into a logic network.
Alan Mishchenko
2014-12-10
1
-15
/
+52
*
Integrating barrier buffers.
Alan Mishchenko
2014-12-08
1
-5
/
+65
*
Added switches '-c' and '-n' to 'init'.
Alan Mishchenko
2014-11-02
1
-1
/
+1
*
Small changes.
Alan Mishchenko
2014-07-29
1
-1
/
+1
*
Adding support for standard-cell mapping.
Alan Mishchenko
2014-07-28
1
-0
/
+111
*
Improvements to CNF generation.
Alan Mishchenko
2014-06-23
1
-2
/
+2
*
merge unfold2
Jiang Long
2014-06-04
1
-1
/
+1
*
Pass file name correctly.
Alan Mishchenko
2014-04-10
1
-3
/
+4
*
Mismatch in bmc3 printout.
Alan Mishchenko
2014-03-30
1
-2
/
+2
*
Updating code to support barrier buffers.
Alan Mishchenko
2014-03-18
1
-0
/
+7
*
Adding barrier buffers.
Alan Mishchenko
2014-03-16
1
-0
/
+5
*
Multi-output property solver.
Alan Mishchenko
2013-10-26
1
-3
/
+4
*
Multi-output property solver.
Alan Mishchenko
2013-10-23
1
-38
/
+44
*
Adding switch &get -m to import mapped network into the &-space.
Alan Mishchenko
2013-09-01
1
-1
/
+1
*
Adding timeout to command 'ind'.
Alan Mishchenko
2013-06-28
1
-2
/
+2
*
Unifying representation of mapping in GIA.
Alan Mishchenko
2013-06-25
1
-1
/
+1
*
Adding a wrapper around clock() for more accurate time counting in ABC.
Alan Mishchenko
2013-05-27
1
-58
/
+58
*
Adding runtime limit per output to multi-output DPR (pdr -H <num_sec>).
Alan Mishchenko
2013-05-03
1
-15
/
+28
*
Adding parameter structure for rarity simulation.
Alan Mishchenko
2013-04-17
1
-2
/
+2
*
Updating 'sim3' to move the design into the last rare state.
Alan Mishchenko
2013-04-01
1
-2
/
+3
*
Added dumping QDIMACS files in command 'qbf'.
Alan Mishchenko
2013-03-27
1
-1
/
+1
*
Adding new features to 'dualrail'.
Alan Mishchenko
2013-02-21
1
-0
/
+3
*
Adding new features to 'dualrail'.
Alan Mishchenko
2013-02-21
1
-0
/
+23
*
Added 'gap timeout' to bmc3 and sim3.
Alan Mishchenko
2013-02-15
1
-2
/
+2
*
Enabled detecting CEXes in multiple POs without stopping (sim3 -a).
Alan Mishchenko
2013-01-23
1
-2
/
+5
*
Enabled detecting CEXes in multiple POs without stopping (sim3 -a).
Alan Mishchenko
2013-01-23
1
-2
/
+2
*
Fixing C++ compilation issues.
Alan Mishchenko
2013-01-08
1
-1
/
+1
*
Enabling multi-output solving in 'pdr'.
Alan Mishchenko
2012-12-09
1
-2
/
+2
*
Enabling multi-output solving in 'pdr'.
Alan Mishchenko
2012-12-09
1
-4
/
+4
*
Enabling multi-output solving in 'pdr'.
Alan Mishchenko
2012-12-09
1
-15
/
+29
*
Enabling multi-output solving in 'pdr'.
Alan Mishchenko
2012-12-09
1
-29
/
+18
*
Enabling multi-output solving in 'pdr'.
Alan Mishchenko
2012-12-09
1
-1
/
+9
*
Enabling multi-output solving in 'pdr'.
Alan Mishchenko
2012-12-09
1
-1
/
+5
*
Isolating BMC code into a separate package.
Alan Mishchenko
2012-11-14
1
-0
/
+1
*
Performance bug fix in choice generation.
Alan Mishchenko
2012-11-09
1
-11
/
+18
*
Integrating GIA with LUT mapping.
Alan Mishchenko
2012-10-24
1
-0
/
+144
*
Extending BLIF parser/write to hangle multi-output cells.
Alan Mishchenko
2012-09-19
1
-2
/
+2
*
Prepared &gla to try abstracting and proving concurrently.
Alan Mishchenko
2012-09-14
1
-1
/
+1
*
Prepared &gla to try abstracting and proving concurrently.
Alan Mishchenko
2012-09-14
1
-9
/
+12
*
Unified print-out of property failures produced by all engines.
Alan Mishchenko
2012-09-09
1
-5
/
+5
*
Added new command &gla_shrink.
Alan Mishchenko
2012-09-04
1
-2
/
+2
*
Added simulation of comb circuits with user-specified patterns in command 'sim'.
Alan Mishchenko
2012-08-24
1
-112
/
+16
*
Fixing assertion mismatch in bmc2.
Alan Mishchenko
2012-07-14
1
-1
/
+1
*
Improvements in the proof-logging SAT solver.
Alan Mishchenko
2012-07-11
1
-2
/
+2
*
Adding several command-line arguments to 'dsat'.
Alan Mishchenko
2012-07-09
1
-3
/
+3
*
Updating memory print-out of &vta and &gla.
Alan Mishchenko
2012-07-08
1
-1
/
+1
*
Adding restart to rarity simulation in sim3 and &sim3.
Alan Mishchenko
2012-07-08
1
-5
/
+5
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