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abci
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abcDar.c
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Age
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*
Prepared &gla to try abstracting and proving concurrently.
Alan Mishchenko
2012-09-14
1
-9
/
+12
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*
Unified print-out of property failures produced by all engines.
Alan Mishchenko
2012-09-09
1
-5
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+5
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*
Added new command &gla_shrink.
Alan Mishchenko
2012-09-04
1
-2
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+2
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*
Added simulation of comb circuits with user-specified patterns in command 'sim'.
Alan Mishchenko
2012-08-24
1
-112
/
+16
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*
Fixing assertion mismatch in bmc2.
Alan Mishchenko
2012-07-14
1
-1
/
+1
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*
Improvements in the proof-logging SAT solver.
Alan Mishchenko
2012-07-11
1
-2
/
+2
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*
Adding several command-line arguments to 'dsat'.
Alan Mishchenko
2012-07-09
1
-3
/
+3
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*
Updating memory print-out of &vta and &gla.
Alan Mishchenko
2012-07-08
1
-1
/
+1
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*
Adding restart to rarity simulation in sim3 and &sim3.
Alan Mishchenko
2012-07-08
1
-5
/
+5
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*
Updating project settings to have simpler include paths.
Alan Mishchenko
2012-07-07
1
-19
/
+19
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*
Fixing time primtouts throughout the code.
Alan Mishchenko
2012-07-07
1
-25
/
+34
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*
Changing the rules of assigning the names when AIG is converted into a logic ↵
Alan Mishchenko
2012-05-11
1
-4
/
+9
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network.
*
Making demiter dump files in the current directory.
Alan Mishchenko
2012-03-26
1
-5
/
+13
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*
Logic sharing for multi-input gates.
Alan Mishchenko
2012-03-25
1
-0
/
+1
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*
Enabled demitering dual-output miters.
Alan Mishchenko
2012-03-23
1
-1
/
+1
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*
Additional features for delay optimization
Alan Mishchenko
2012-03-21
1
-0
/
+9
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*
Renamed Aig_ObjPioNum to be Aig_ObjCioId.
Alan Mishchenko
2012-03-09
1
-2
/
+2
|
*
Renamed Aig_ObjIsPi/Po to be ...Ci/Co and Aig_Man(Pi/Po)Num to be ...(Ci/Co)...
Alan Mishchenko
2012-03-09
1
-14
/
+14
|
*
Renamed Aig_ManForEachPi/Po to be ...Ci/Co and Aig_ObjCreatePi/Po to be ↵
Alan Mishchenko
2012-03-09
1
-16
/
+16
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...Ci/Co.
*
Redirecting printf messages.
Alan Mishchenko
2012-03-02
1
-181
/
+181
|
*
Making BMC engines (bmc2, bmc3) to perform OR-decomposition by default (bug ↵
Alan Mishchenko
2012-02-25
1
-1
/
+1
|
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fix).
*
Making BMC engines (bmc2, bmc3) to perform OR-decomposition by default.
Alan Mishchenko
2012-02-24
1
-8
/
+11
|
*
Making BMC engines (bmc2, bmc3) to perform OR-decomposition by default.
Alan Mishchenko
2012-02-24
1
-1
/
+8
|
*
Making BMC engines (bmc2, bmc3) to perform OR-decomposition by default.
Alan Mishchenko
2012-02-24
1
-51
/
+165
|
*
Silencing some of the gcc warnings.
Alan Mishchenko
2012-02-16
1
-3
/
+3
|
*
Added returning counter-example after BMC, which was recently added to 'dprove'.
Alan Mishchenko
2012-01-23
1
-0
/
+4
|
*
Major restructuring of the code.
Alan Mishchenko
2012-01-21
1
-23
/
+23
|
*
Replaced 'bmc' by 'bmc2' in 'dprove'. Added switches to 'dprove' to control ↵
Alan Mishchenko
2012-01-19
1
-13
/
+15
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BMC frames and conflicts.
*
Started experiments with a new solver.
Alan Mishchenko
2011-11-25
1
-3
/
+3
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*
Fixed the overflow timeout problem in bmc/bmc2/bmc3/int/pdr/sim, etc.
Alan Mishchenko
2011-10-31
1
-5
/
+5
|
*
Changes to CNF generation code.
Alan Mishchenko
2011-10-17
1
-5
/
+18
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*
Sequential cleanup with symbolic/ternary simulation.
Alan Mishchenko
2011-08-25
1
-1
/
+1
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*
Sequential cleanup with symbolic/ternary simulation.
Alan Mishchenko
2011-08-24
1
-8
/
+8
|
*
Several bug fixes.
Alan Mishchenko
2011-08-02
1
-4
/
+14
|
*
Enabled saving vector of counter-examples in the ABC framework.
Alan Mishchenko
2011-08-02
1
-3
/
+3
|
*
Improvements to 'bmc3' (start frame; stop when all POs are SAT; stop when ↵
Alan Mishchenko
2011-07-31
1
-6
/
+4
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2^nRegs frames are completed).
*
Added generation of counter-examples to induction in 'ind'.
Alan Mishchenko
2011-07-30
1
-4
/
+10
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*
Changes to enable smarter simulation.
Alan Mishchenko
2011-07-30
1
-47
/
+1
|
*
Changes to enable smarter simulation.
Alan Mishchenko
2011-07-30
1
-2
/
+2
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*
Improving and updating the abstraction code.
Alan Mishchenko
2011-07-29
1
-68
/
+1
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*
Adding &equiv3, a new way of refining equivalence classes.
Alan Mishchenko
2011-07-22
1
-1
/
+47
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*
Changes to enable smarter simulation.
Alan Mishchenko
2011-07-21
1
-0
/
+46
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*
New demitering features.
Alan Mishchenko
2011-07-20
1
-0
/
+53
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*
Added a new demitering feature for dual-output miters.
Alan Mishchenko
2011-07-02
1
-0
/
+68
|
*
Added new command 'outdec'.
Alan Mishchenko
2011-05-19
1
-0
/
+30
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*
Improvements in sequential verification.
Alan Mishchenko
2011-05-06
1
-5
/
+32
|
*
Adding SAT-solver-level timeouts to the BMC engines.
Alan Mishchenko
2011-04-08
1
-26
/
+32
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*
Several bug fixes and other improvements.
Alan Mishchenko
2011-03-12
1
-15
/
+0
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*
Made abc.h independent of CUDD and Extra.
Alan Mishchenko
2011-03-03
1
-2
/
+2
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*
Unified the use of counter-examples in three packages.
Alan Mishchenko
2011-02-13
1
-13
/
+12
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