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* Bug fix in the timing manager.Alan Mishchenko2021-09-061-28/+30
* Various changes.Alan Mishchenko2021-09-041-1/+1
* Various changes.Alan Mishchenko2021-09-021-2/+16
* Allow &mfs to work on sequential AIGs.Alan Mishchenko2021-08-241-1/+10
* Compiler warnings.Alan Mishchenko2021-08-232-2/+4
* Support of pair-wise miter and other changes.Alan Mishchenko2021-08-221-2/+19
* Extending &trim to trim structurally equivalent primary outputs.Alan Mishchenko2021-08-191-3/+14
* Improving AIG to Verilog converter.Alan Mishchenko2021-08-171-3/+8
* Suggested changes to collect and pass timing information (unused variable).Alan Mishchenko2021-08-121-1/+1
* Suggested changes to collect and pass timing information (compiler issues).Alan Mishchenko2021-08-121-7/+5
* Suggested changes to collect and pass timing information.Alan Mishchenko2021-08-121-8/+50
* Making &cec support the miter circuit.Alan Mishchenko2021-08-051-0/+14
* Adding node ordering options to command &dfs.Alan Mishchenko2021-08-051-22/+13
* Experiments with LUT mapping for small functions.Alan Mishchenko2021-08-021-7/+3
* Experiments with LUT mapping for small functions.Alan Mishchenko2021-08-011-1/+2
* Upgrading choice computation.Alan Mishchenko2021-07-312-21/+31
* Experiments with cofactoring.Alan Mishchenko2021-07-311-6/+23
* Experimental simulation commands.Alan Mishchenko2021-07-251-0/+180
* Command to move CI/CO names.Alan Mishchenko2021-07-161-2/+3
* Command to move CI/CO names.Alan Mishchenko2021-07-161-0/+63
* Experiments with LUT mapping for small functions.Alan Mishchenko2021-07-131-3/+14
* Experiments with CEC.Alan Mishchenko2021-07-101-4/+26
* Experiments with MUX decomposition.Alan Mishchenko2021-07-081-1/+55
* Adding place holder file for resub experiments.Alan Mishchenko2021-06-241-6/+7
* Experiments with LUT mapping for small functions.Alan Mishchenko2021-06-191-25/+44
* Experiments with cut computation.Alan Mishchenko2021-06-051-0/+1
* Disabled special handling of 2-input LUTs.Alan Mishchenko2021-06-031-1/+1
* Updating LUT synthesis code.Alan Mishchenko2021-05-252-35/+120
* Adding command &extract.Alan Mishchenko2021-05-182-1/+84
* Updating LUT synthesis code.Alan Mishchenko2021-05-163-45/+344
* Adding switch muxes -a to create networks of ADDs.Alan Mishchenko2021-05-152-13/+36
* Updating LUT synthesis code.Alan Mishchenko2021-05-111-14/+25
* Disable cube-sort when deriving SOPs.Alan Mishchenko2021-05-117-10/+19
* Updating LUT synthesis code.Alan Mishchenko2021-05-111-9/+91
* Updating LUT synthesis code.Alan Mishchenko2021-05-081-2/+3
* Fixing mismatch in &cec -x which should return undecided rather than non-equi...Alan Mishchenko2021-05-081-1/+1
* Experiments with LUT mapping for small functions.Alan Mishchenko2021-05-012-4/+73
* Several changes for standard mapping.Alan Mishchenko2021-04-281-2/+4
* Passing node labels.Alan Mishchenko2021-04-261-0/+1
* Computing sum of PO support sizes.Alan Mishchenko2021-04-091-1/+2
* An option to extend the number of primary inputs.Alan Mishchenko2021-03-281-2/+32
* Compiler warnings.Alan Mishchenko2021-03-281-3/+3
* Command &iwls21test for evaluating the results of 2021 IWLS Contest.Alan Mishchenko2021-03-281-0/+92
* Adding a random seed to control randomness in 'permute' (correction).Alan Mishchenko2021-03-111-2/+2
* Adding a random seed to control randomness in 'permute'.Alan Mishchenko2021-03-111-2/+17
* Compiler warnings.Alan Mishchenko2020-12-211-0/+1
* Adding solver type in &sat.Alan Mishchenko2020-12-161-2/+14
* Adding generation of combinational speculative miters.Alan Mishchenko2020-12-161-3/+17
* Adding switch to replace proved outputs by const0.Alan Mishchenko2020-12-161-5/+9
* Deriving equivalent nets from proved equivalences.Alan Mishchenko2020-12-091-1/+28
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