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* Bug fix in 'gen -b'.Alan Mishchenko2018-07-081-3/+3
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* Updating command 'majgen'.Alan Mishchenko2018-07-041-5/+9
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* Bug fix.Alan Mishchenko2018-07-041-1/+0
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* Generating adder-trees using 'gen -b -A <num> -N <num> <file>.v'.Alan Mishchenko2018-07-042-2/+81
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* Adding command 'majgen'.Alan Mishchenko2018-07-041-0/+54
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* Enabling user-specified output signature in &polyn.Alan Mishchenko2018-06-131-6/+32
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* Experiments with path enumeration.Alan Mishchenko2018-06-101-2/+60
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* Adding switch 'clp -o' to reverse initial variable ordering.Alan Mishchenko2018-06-0715-33/+38
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* Experiments with path enumeration.Alan Mishchenko2018-06-061-1/+1
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* Adding command print_mint.Alan Mishchenko2018-06-041-0/+64
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* Simple BDD package.Alan Mishchenko2018-05-231-1/+3
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* Bug fix in &sat -x.Alan Mishchenko2018-05-071-2/+3
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* Adding &sat -x to save CEXes for multi-output combinational miters.Alan Mishchenko2018-05-061-4/+33
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* Adding switch &w -p to dump AIG in a Verilog file.Alan Mishchenko2018-04-251-2/+9
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* The ECO code.Alan Mishchenko2018-04-251-2/+11
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* The ECO code.Alan Mishchenko2018-04-251-6/+6
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* Typo in the command description.Alan Mishchenko2018-04-251-5/+5
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* Memory abstraction.Alan Mishchenko2018-04-151-0/+2
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* Adding new NPN code developed by XueGong Zhou at Fudan University.Alan Mishchenko2018-03-252-7/+29
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* Adding switch 'scorr -f' to dump inductive invariant as an AIG.Alan Mishchenko2018-03-221-5/+14
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* Experiments with LUT mapping.Alan Mishchenko2018-02-101-5/+18
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* Improvements to NDR to represent hierarchical designs.Alan Mishchenko2018-02-051-2/+1
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* Improvements to NDR to represent hierarchical designs.Alan Mishchenko2018-02-051-1/+2
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* Experiments with circuit-based SAT.Alan Mishchenko2018-01-271-4/+15
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* Experiments with SAT-based simulation.Alan Mishchenko2018-01-251-1/+1
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* Updates to exact synthesis commands.Alan Mishchenko2018-01-191-4/+26
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* New command 'testexact'.Alan Mishchenko2018-01-041-0/+51
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* New exact synthesis command 'allexact'.Alan Mishchenko2017-12-301-2/+2
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* New exact synthesis command 'allexact'.Alan Mishchenko2017-12-281-1/+170
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* Adding parameter structure to 'twoexact' and 'lutexact'.Alan Mishchenko2017-12-061-59/+71
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* An improvement to 'twoexact' and 'lutexact'.Alan Mishchenko2017-12-061-0/+27
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* An improvement to 'twoexact' and 'lutexact'.Alan Mishchenko2017-12-061-2/+2
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* Switch -a to use only AND-gates in 'twoexact' and 'lutexact'.Alan Mishchenko2017-12-061-14/+22
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* New command 'lutexact'.Alan Mishchenko2017-12-051-0/+104
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* Adding switch -a to 'write_verilog' to write factored forms without XORs and ↵Alan Mishchenko2017-12-031-1/+1
| | | | MUXes.
* Changes to make GIA structural hashing use a dedicated array instead of ↵Alan Mishchenko2017-11-131-2/+2
| | | | pObj->Value.
* Adding API to dump MiniAIG into a Verilog file and other small changes.Alan Mishchenko2017-10-221-1/+1
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* Adding random search in exact synthesis.Alan Mishchenko2017-10-201-6/+23
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* Integrating old SAT solver into majexact and twoexact.Alan Mishchenko2017-10-191-11/+27
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* Integrating Glucose into &qbf.Alan Mishchenko2017-10-171-6/+11
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* Fix the build.Alan Mishchenko2017-10-111-1/+0
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* Another variation on exact synthesis.Alan Mishchenko2017-10-111-1/+80
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* Adding printout of slack distribution for mapped networks.Alan Mishchenko2017-10-021-3/+7
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* Exact synthesis of majority gates.Alan Mishchenko2017-10-011-14/+18
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* Exact synthesis of majority gates.Alan Mishchenko2017-10-011-0/+75
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* Maintenance and updates.Alan Mishchenko2017-09-241-4/+9
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* Maintenance and updates.Alan Mishchenko2017-09-201-11/+22
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* Enabling Glucose in SAT sweeping: &fraig -g.Alan Mishchenko2017-09-181-3/+10
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* Adding support for Dimacs input to &satoko.Alan Mishchenko2017-09-161-6/+14
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* Experiment with mapping.Alan Mishchenko2017-09-151-1/+80
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