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* Adding command print_mint.Alan Mishchenko2018-06-041-0/+64
* Simple BDD package.Alan Mishchenko2018-05-231-1/+3
* Bug fix in &sat -x.Alan Mishchenko2018-05-071-2/+3
* Adding &sat -x to save CEXes for multi-output combinational miters.Alan Mishchenko2018-05-061-4/+33
* Adding switch &w -p to dump AIG in a Verilog file.Alan Mishchenko2018-04-251-2/+9
* The ECO code.Alan Mishchenko2018-04-251-2/+11
* The ECO code.Alan Mishchenko2018-04-251-6/+6
* Typo in the command description.Alan Mishchenko2018-04-251-5/+5
* Memory abstraction.Alan Mishchenko2018-04-151-0/+2
* Adding new NPN code developed by XueGong Zhou at Fudan University.Alan Mishchenko2018-03-252-7/+29
* Adding switch 'scorr -f' to dump inductive invariant as an AIG.Alan Mishchenko2018-03-221-5/+14
* Experiments with LUT mapping.Alan Mishchenko2018-02-101-5/+18
* Improvements to NDR to represent hierarchical designs.Alan Mishchenko2018-02-051-2/+1
* Improvements to NDR to represent hierarchical designs.Alan Mishchenko2018-02-051-1/+2
* Experiments with circuit-based SAT.Alan Mishchenko2018-01-271-4/+15
* Experiments with SAT-based simulation.Alan Mishchenko2018-01-251-1/+1
* Updates to exact synthesis commands.Alan Mishchenko2018-01-191-4/+26
* New command 'testexact'.Alan Mishchenko2018-01-041-0/+51
* New exact synthesis command 'allexact'.Alan Mishchenko2017-12-301-2/+2
* New exact synthesis command 'allexact'.Alan Mishchenko2017-12-281-1/+170
* Adding parameter structure to 'twoexact' and 'lutexact'.Alan Mishchenko2017-12-061-59/+71
* An improvement to 'twoexact' and 'lutexact'.Alan Mishchenko2017-12-061-0/+27
* An improvement to 'twoexact' and 'lutexact'.Alan Mishchenko2017-12-061-2/+2
* Switch -a to use only AND-gates in 'twoexact' and 'lutexact'.Alan Mishchenko2017-12-061-14/+22
* New command 'lutexact'.Alan Mishchenko2017-12-051-0/+104
* Adding switch -a to 'write_verilog' to write factored forms without XORs and ...Alan Mishchenko2017-12-031-1/+1
* Changes to make GIA structural hashing use a dedicated array instead of pObj-...Alan Mishchenko2017-11-131-2/+2
* Adding API to dump MiniAIG into a Verilog file and other small changes.Alan Mishchenko2017-10-221-1/+1
* Adding random search in exact synthesis.Alan Mishchenko2017-10-201-6/+23
* Integrating old SAT solver into majexact and twoexact.Alan Mishchenko2017-10-191-11/+27
* Integrating Glucose into &qbf.Alan Mishchenko2017-10-171-6/+11
* Fix the build.Alan Mishchenko2017-10-111-1/+0
* Another variation on exact synthesis.Alan Mishchenko2017-10-111-1/+80
* Adding printout of slack distribution for mapped networks.Alan Mishchenko2017-10-021-3/+7
* Exact synthesis of majority gates.Alan Mishchenko2017-10-011-14/+18
* Exact synthesis of majority gates.Alan Mishchenko2017-10-011-0/+75
* Maintenance and updates.Alan Mishchenko2017-09-241-4/+9
* Maintenance and updates.Alan Mishchenko2017-09-201-11/+22
* Enabling Glucose in SAT sweeping: &fraig -g.Alan Mishchenko2017-09-181-3/+10
* Adding support for Dimacs input to &satoko.Alan Mishchenko2017-09-161-6/+14
* Experiment with mapping.Alan Mishchenko2017-09-151-1/+80
* Updates to &bmcs to help debugging.Alan Mishchenko2017-09-121-2/+2
* Adding switch '-c' to 'dsec' to disable internal netlist check.Alan Mishchenko2017-09-091-17/+21
* Disabling CNF simplification in &bmcs -g.Alan Mishchenko2017-09-071-2/+2
* Trying to enable CNF simplification in &bmcs -g.Alan Mishchenko2017-09-071-2/+7
* Integrating Glucose into bmc3 -g.Alan Mishchenko2017-09-061-2/+6
* Integrating Glucose into &bmcs -g.Alan Mishchenko2017-09-061-5/+11
* Renaming command-line option '-s' to be '-q' in 'pdr'.Alan Mishchenko2017-09-061-4/+4
* Several changes to various packages.Alan Mishchenko2017-09-042-1/+29
* Integrating Satoko into 'bmc' and 'bmc2'.Alan Mishchenko2017-08-162-12/+24
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