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* Various changes.Alan Mishchenko2021-09-021-2/+16
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* Allow &mfs to work on sequential AIGs.Alan Mishchenko2021-08-241-1/+10
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* Compiler warnings.Alan Mishchenko2021-08-232-2/+4
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* Support of pair-wise miter and other changes.Alan Mishchenko2021-08-221-2/+19
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* Extending &trim to trim structurally equivalent primary outputs.Alan Mishchenko2021-08-191-3/+14
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* Improving AIG to Verilog converter.Alan Mishchenko2021-08-171-3/+8
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* Suggested changes to collect and pass timing information (unused variable).Alan Mishchenko2021-08-121-1/+1
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* Suggested changes to collect and pass timing information (compiler issues).Alan Mishchenko2021-08-121-7/+5
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* Suggested changes to collect and pass timing information.Alan Mishchenko2021-08-121-8/+50
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* Making &cec support the miter circuit.Alan Mishchenko2021-08-051-0/+14
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* Adding node ordering options to command &dfs.Alan Mishchenko2021-08-051-22/+13
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* Experiments with LUT mapping for small functions.Alan Mishchenko2021-08-021-7/+3
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* Experiments with LUT mapping for small functions.Alan Mishchenko2021-08-011-1/+2
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* Upgrading choice computation.Alan Mishchenko2021-07-312-21/+31
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* Experiments with cofactoring.Alan Mishchenko2021-07-311-6/+23
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* Experimental simulation commands.Alan Mishchenko2021-07-251-0/+180
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* Command to move CI/CO names.Alan Mishchenko2021-07-161-2/+3
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* Command to move CI/CO names.Alan Mishchenko2021-07-161-0/+63
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* Experiments with LUT mapping for small functions.Alan Mishchenko2021-07-131-3/+14
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* Experiments with CEC.Alan Mishchenko2021-07-101-4/+26
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* Experiments with MUX decomposition.Alan Mishchenko2021-07-081-1/+55
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* Adding place holder file for resub experiments.Alan Mishchenko2021-06-241-6/+7
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* Experiments with LUT mapping for small functions.Alan Mishchenko2021-06-191-25/+44
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* Experiments with cut computation.Alan Mishchenko2021-06-051-0/+1
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* Disabled special handling of 2-input LUTs.Alan Mishchenko2021-06-031-1/+1
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* Updating LUT synthesis code.Alan Mishchenko2021-05-252-35/+120
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* Adding command &extract.Alan Mishchenko2021-05-182-1/+84
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* Updating LUT synthesis code.Alan Mishchenko2021-05-163-45/+344
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* Adding switch muxes -a to create networks of ADDs.Alan Mishchenko2021-05-152-13/+36
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* Updating LUT synthesis code.Alan Mishchenko2021-05-111-14/+25
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* Disable cube-sort when deriving SOPs.Alan Mishchenko2021-05-117-10/+19
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* Updating LUT synthesis code.Alan Mishchenko2021-05-111-9/+91
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* Updating LUT synthesis code.Alan Mishchenko2021-05-081-2/+3
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* Fixing mismatch in &cec -x which should return undecided rather than ↵Alan Mishchenko2021-05-081-1/+1
| | | | non-equivalent when the miter cannot be reduced to constant 0.
* Experiments with LUT mapping for small functions.Alan Mishchenko2021-05-012-4/+73
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* Several changes for standard mapping.Alan Mishchenko2021-04-281-2/+4
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* Passing node labels.Alan Mishchenko2021-04-261-0/+1
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* Computing sum of PO support sizes.Alan Mishchenko2021-04-091-1/+2
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* An option to extend the number of primary inputs.Alan Mishchenko2021-03-281-2/+32
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* Compiler warnings.Alan Mishchenko2021-03-281-3/+3
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* Command &iwls21test for evaluating the results of 2021 IWLS Contest.Alan Mishchenko2021-03-281-0/+92
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* Adding a random seed to control randomness in 'permute' (correction).Alan Mishchenko2021-03-111-2/+2
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* Adding a random seed to control randomness in 'permute'.Alan Mishchenko2021-03-111-2/+17
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* Compiler warnings.Alan Mishchenko2020-12-211-0/+1
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* Adding solver type in &sat.Alan Mishchenko2020-12-161-2/+14
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* Adding generation of combinational speculative miters.Alan Mishchenko2020-12-161-3/+17
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* Adding switch to replace proved outputs by const0.Alan Mishchenko2020-12-161-5/+9
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* Deriving equivalent nets from proved equivalences.Alan Mishchenko2020-12-091-1/+28
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* Adding timeout to several commands.Alan Mishchenko2020-12-071-10/+34
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* Renaming one command.Alan Mishchenko2020-11-231-3/+3
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