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yosys-experimental
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Author
Age
Files
Lines
*
Changing static to extern for two procedures.
Alan Mishchenko
2021-10-17
1
-2
/
+2
*
Experiments with SAT solving.
Alan Mishchenko
2021-10-09
1
-3
/
+22
*
New command &stochsyn for stochastic synthesis.
Alan Mishchenko
2021-10-06
1
-0
/
+103
*
Changing declaration of Vec_Ptr_t sorting function to satisfy some compilers.
Alan Mishchenko
2021-09-26
7
-7
/
+7
*
Two rare corner-case bugs in &if mapper.
Alan Mishchenko
2021-09-26
1
-1
/
+5
*
Adding command &reshape.
Alan Mishchenko
2021-09-21
1
-6
/
+11
*
Adding command &reshape.
Alan Mishchenko
2021-09-21
1
-0
/
+63
*
Removing unused command.
Alan Mishchenko
2021-09-21
1
-155
/
+0
*
Various changes.
Alan Mishchenko
2021-09-21
1
-5
/
+9
*
Improving MiniAIG and name manager.
Alan Mishchenko
2021-09-16
1
-1
/
+1
*
Enable command 'pipe' for pipelining.
Alan Mishchenko
2021-09-13
2
-3
/
+12
*
Disabling command print_mint when CUDD is not used.
Alan Mishchenko
2021-09-07
1
-0
/
+7
*
Bug fix in the timing manager.
Alan Mishchenko
2021-09-06
1
-28
/
+30
*
Various changes.
Alan Mishchenko
2021-09-04
1
-1
/
+1
*
Various changes.
Alan Mishchenko
2021-09-02
1
-2
/
+16
*
Allow &mfs to work on sequential AIGs.
Alan Mishchenko
2021-08-24
1
-1
/
+10
*
Compiler warnings.
Alan Mishchenko
2021-08-23
2
-2
/
+4
*
Support of pair-wise miter and other changes.
Alan Mishchenko
2021-08-22
1
-2
/
+19
*
Extending &trim to trim structurally equivalent primary outputs.
Alan Mishchenko
2021-08-19
1
-3
/
+14
*
Improving AIG to Verilog converter.
Alan Mishchenko
2021-08-17
1
-3
/
+8
*
Suggested changes to collect and pass timing information (unused variable).
Alan Mishchenko
2021-08-12
1
-1
/
+1
*
Suggested changes to collect and pass timing information (compiler issues).
Alan Mishchenko
2021-08-12
1
-7
/
+5
*
Suggested changes to collect and pass timing information.
Alan Mishchenko
2021-08-12
1
-8
/
+50
*
Making &cec support the miter circuit.
Alan Mishchenko
2021-08-05
1
-0
/
+14
*
Adding node ordering options to command &dfs.
Alan Mishchenko
2021-08-05
1
-22
/
+13
*
Experiments with LUT mapping for small functions.
Alan Mishchenko
2021-08-02
1
-7
/
+3
*
Experiments with LUT mapping for small functions.
Alan Mishchenko
2021-08-01
1
-1
/
+2
*
Upgrading choice computation.
Alan Mishchenko
2021-07-31
2
-21
/
+31
*
Experiments with cofactoring.
Alan Mishchenko
2021-07-31
1
-6
/
+23
*
Experimental simulation commands.
Alan Mishchenko
2021-07-25
1
-0
/
+180
*
Command to move CI/CO names.
Alan Mishchenko
2021-07-16
1
-2
/
+3
*
Command to move CI/CO names.
Alan Mishchenko
2021-07-16
1
-0
/
+63
*
Experiments with LUT mapping for small functions.
Alan Mishchenko
2021-07-13
1
-3
/
+14
*
Experiments with CEC.
Alan Mishchenko
2021-07-10
1
-4
/
+26
*
Experiments with MUX decomposition.
Alan Mishchenko
2021-07-08
1
-1
/
+55
*
Adding place holder file for resub experiments.
Alan Mishchenko
2021-06-24
1
-6
/
+7
*
Experiments with LUT mapping for small functions.
Alan Mishchenko
2021-06-19
1
-25
/
+44
*
Experiments with cut computation.
Alan Mishchenko
2021-06-05
1
-0
/
+1
*
Disabled special handling of 2-input LUTs.
Alan Mishchenko
2021-06-03
1
-1
/
+1
*
Updating LUT synthesis code.
Alan Mishchenko
2021-05-25
2
-35
/
+120
*
Adding command &extract.
Alan Mishchenko
2021-05-18
2
-1
/
+84
*
Updating LUT synthesis code.
Alan Mishchenko
2021-05-16
3
-45
/
+344
*
Adding switch muxes -a to create networks of ADDs.
Alan Mishchenko
2021-05-15
2
-13
/
+36
*
Updating LUT synthesis code.
Alan Mishchenko
2021-05-11
1
-14
/
+25
*
Disable cube-sort when deriving SOPs.
Alan Mishchenko
2021-05-11
7
-10
/
+19
*
Updating LUT synthesis code.
Alan Mishchenko
2021-05-11
1
-9
/
+91
*
Updating LUT synthesis code.
Alan Mishchenko
2021-05-08
1
-2
/
+3
*
Fixing mismatch in &cec -x which should return undecided rather than non-equi...
Alan Mishchenko
2021-05-08
1
-1
/
+1
*
Experiments with LUT mapping for small functions.
Alan Mishchenko
2021-05-01
2
-4
/
+73
*
Several changes for standard mapping.
Alan Mishchenko
2021-04-28
1
-2
/
+4
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