summaryrefslogtreecommitdiffstats
path: root/src/base/io/io.c
Commit message (Expand)AuthorAgeFilesLines
* Improving truth table handling.Alan Mishchenko2022-02-161-0/+10
* Improving truth table handling.Alan Mishchenko2022-02-031-19/+24
* Updating LUT synthesis code.Alan Mishchenko2021-05-161-5/+15
* Adding an option to write Verilog with LUT instances (compiler warnings).Alan Mishchenko2020-10-311-1/+1
* Adding an option to write Verilog with LUT instances.Alan Mishchenko2020-10-311-3/+19
* Fixing a clang error related to 'unlink'.Alan Mishchenko2020-10-091-0/+3
* New command 'read_sf'.Alan Mishchenko2020-10-011-0/+73
* Ongoing changes to the simulator.Alan Mishchenko2020-03-091-0/+2
* Adding CNF variable mapping rules.Alan Mishchenko2020-01-181-0/+11
* Updates to JSON parser.Alan Mishchenko2019-12-021-6/+12
* Adding logfile dump to print_status.Alan Mishchenko2019-11-251-0/+26
* Dumping multiple counter-examples.Alan Mishchenko2019-11-191-1/+1
* Dumping multiple counter-examples.Alan Mishchenko2019-11-191-1/+1
* Dumping multiple counter-examples.Alan Mishchenko2019-11-191-104/+139
* Adding synonym of 'read_dsd'.Alan Mishchenko2019-06-201-0/+1
* Modifying 'write_truth' to dump truth table in hex.Alan Mishchenko2019-05-071-3/+11
* Adding switch 'read_truth -f <file_name>' to read truth table from file.Alan Mishchenko2019-04-151-9/+22
* Add skip feature to CEX printing.Alan Mishchenko2019-02-081-1/+9
* Exploring other ways of CEX writing.Alan Mishchenko2019-01-211-5/+51
* Undoing some recent changes for improved CEX writing.Alan Mishchenko2019-01-211-65/+8
* Fixing the problem with outputting word-level CEXes after retiming.Alan Mishchenko2019-01-181-12/+28
* Fixing the problem with outputting word-level CEXes after retiming.Alan Mishchenko2019-01-171-19/+37
* Fixing the problem with outputting word-level CEXes.Alan Mishchenko2019-01-161-1/+24
* Various usability changes.Alan Mishchenko2018-11-181-3/+14
* Adding switch to 'write_pla' to write random onset minterms of the first PO f...Alan Mishchenko2018-09-281-8/+31
* Integrating SAT-based CEX minimization (bug fix).Alan Mishchenko2018-03-251-2/+2
* Integrating SAT-based CEX minimization.Alan Mishchenko2018-03-251-8/+20
* Adding switch -a to 'write_verilog' to write factored forms without XORs and ...Alan Mishchenko2017-12-031-3/+16
* Adding PDR with abstraction.Alan Mishchenko2017-02-101-1/+1
* Improving CEX minimization.Alan Mishchenko2017-02-101-1/+1
* Updates to arithmetic verification.Alan Mishchenko2017-01-301-1/+1
* Commenting out bailout in 'print_cex' when CEX has latches initialized to 1.Alan Mishchenko2016-11-301-1/+2
* Parser for JSON format.Alan Mishchenko2016-10-251-2/+115
* New multi-output PLA reader and preprocessor (read_plamo) (added dist-1 merge).Alan Mishchenko2016-06-161-5/+9
* New multi-output PLA reader and preprocessor (read_plamo).Alan Mishchenko2016-06-161-0/+52
* Detecting properties of internal nodes.Alan Mishchenko2016-06-121-0/+58
* Adding 'read_pla -d' to read dc-set along with on-set (useful to derive offset).Alan Mishchenko2016-05-121-5/+9
* Updating GIG parser.Alan Mishchenko2016-05-011-1/+1
* Added Exorcism package, reading ESOP (read_pla -x file.esop) and deriving AIG...Alan Mishchenko2016-04-111-5/+9
* Adding switch '-b' in 'read_pla'.Alan Mishchenko2015-03-181-9/+9
* Fixed a typo in variable names.Alan Mishchenko2015-02-071-1/+1
* Esperiments with MO PLA optimization.Alan Mishchenko2015-02-031-4/+8
* Integrating barrier buffers.Alan Mishchenko2014-12-131-2/+1
* Generation of barrier-buffers for hierarchical design.Alan Mishchenko2014-11-111-6/+9
* Adding cyclicity check for netlist with boxes.Alan Mishchenko2014-11-101-3/+22
* Adding features to CNF generation.Alan Mishchenko2014-09-281-6/+16
* New word-level representation package.Alan Mishchenko2014-09-121-57/+0
* Bug fix in transferring timing info.Alan Mishchenko2014-09-091-0/+57
* Improvements to power-aware mapping.Alan Mishchenko2014-06-231-1/+1
* Improvements to CNF generation.Alan Mishchenko2014-06-231-1/+1
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-19 23:51:36 +0000