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path: root/src/base/io/io.c
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* Improving CEX minimization.Alan Mishchenko2017-02-101-1/+1
* Updates to arithmetic verification.Alan Mishchenko2017-01-301-1/+1
* Commenting out bailout in 'print_cex' when CEX has latches initialized to 1.Alan Mishchenko2016-11-301-1/+2
* Parser for JSON format.Alan Mishchenko2016-10-251-2/+115
* New multi-output PLA reader and preprocessor (read_plamo) (added dist-1 merge).Alan Mishchenko2016-06-161-5/+9
* New multi-output PLA reader and preprocessor (read_plamo).Alan Mishchenko2016-06-161-0/+52
* Detecting properties of internal nodes.Alan Mishchenko2016-06-121-0/+58
* Adding 'read_pla -d' to read dc-set along with on-set (useful to derive offset).Alan Mishchenko2016-05-121-5/+9
* Updating GIG parser.Alan Mishchenko2016-05-011-1/+1
* Added Exorcism package, reading ESOP (read_pla -x file.esop) and deriving AIG...Alan Mishchenko2016-04-111-5/+9
* Adding switch '-b' in 'read_pla'.Alan Mishchenko2015-03-181-9/+9
* Fixed a typo in variable names.Alan Mishchenko2015-02-071-1/+1
* Esperiments with MO PLA optimization.Alan Mishchenko2015-02-031-4/+8
* Integrating barrier buffers.Alan Mishchenko2014-12-131-2/+1
* Generation of barrier-buffers for hierarchical design.Alan Mishchenko2014-11-111-6/+9
* Adding cyclicity check for netlist with boxes.Alan Mishchenko2014-11-101-3/+22
* Adding features to CNF generation.Alan Mishchenko2014-09-281-6/+16
* New word-level representation package.Alan Mishchenko2014-09-121-57/+0
* Bug fix in transferring timing info.Alan Mishchenko2014-09-091-0/+57
* Improvements to power-aware mapping.Alan Mishchenko2014-06-231-1/+1
* Improvements to CNF generation.Alan Mishchenko2014-06-231-1/+1
* Improvements to CNF generation.Alan Mishchenko2014-06-231-9/+35
* Added quick GIG parser.Alan Mishchenko2014-06-191-0/+59
* add an option to write_cex to write the CEX in AIGER 1.9 format.Baruch Sterin2014-05-121-1/+11
* Added dumping original object names into a file.Alan Mishchenko2014-04-261-2/+12
* Renamed Abc_Lib_t into Abc_Des_t and removed some dead code.Alan Mishchenko2014-04-091-232/+0
* Better CEX minimization and renaming of write_counter into write_cex.Alan Mishchenko2014-04-041-12/+27
* Adding barrier buffers.Alan Mishchenko2014-03-161-17/+27
* Changes to LUT mappers.Alan Mishchenko2014-03-091-0/+4
* Adding check for the presence of precomputed data.Alan Mishchenko2013-12-291-0/+5
* New command &write_cnf.Alan Mishchenko2013-12-181-0/+66
* Debugging and finetuning the flow.Alan Mishchenko2013-09-171-0/+2
* Unifying standard cell library representations.Alan Mishchenko2013-09-171-1/+1
* New MFS package.Alan Mishchenko2013-05-241-4/+4
* Improvements to LMS code.Alan Mishchenko2012-11-061-2/+2
* Adding binary file dumping for truth tables.Alan Mishchenko2012-10-251-1/+1
* Adding binary file dumping for truth tables.Alan Mishchenko2012-10-251-4/+18
* Added hierarchical BLIF output for mapping with LUT structures (write_blif -a...Alan Mishchenko2012-10-241-3/+8
* Added command to transform GIA into the file with truth tables for each output.Alan Mishchenko2012-10-101-0/+77
* Replacing 'st_table' by 'st__table' to resolve linker problems.Alan Mishchenko2012-09-291-1/+1
* Cleaned up interfaces of genlib/liberty/supergate reading/writing.Alan Mishchenko2012-09-251-5/+18
* Changed printouts in a few places in supergate computation.Alan Mishchenko2012-09-241-0/+2
* Added simplification before the concurrent call to PDR.Alan Mishchenko2012-09-201-2/+2
* Modified 'read' to read all types of libraries (genlib, liberty, scl).Alan Mishchenko2012-09-201-0/+2
* Modified 'read' to read all types of libraries (genlib, liberty, scl).Alan Mishchenko2012-09-201-2/+16
* Fixes to Verilog parser.Alan Mishchenko2012-09-201-0/+6
* Created new abstraction package from the code that was all over the place.Alan Mishchenko2012-09-151-0/+1
* Updating project settings to have simpler include paths.Alan Mishchenko2012-07-071-3/+3
* Diabling compact AIGER writing by default.Alan Mishchenko2012-07-071-1/+1
* Graph isomorphism checking code.Alan Mishchenko2012-02-111-4/+29
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