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* Suggested changes to collect and pass timing information.Alan Mishchenko2021-08-121-5/+14
* Updating LUT synthesis code.Alan Mishchenko2021-05-162-16/+89
* Disable cube-sort when deriving SOPs.Alan Mishchenko2021-05-111-2/+2
* Updating LUT synthesis code.Alan Mishchenko2021-05-111-1/+1
* Making sure read_bench can read nodes up to 15 inputs.Alan Mishchenko2021-04-302-5/+6
* Passing node labels.Alan Mishchenko2021-04-261-0/+8
* Trying to explicitly compute don't-cares during optimization.Alan Mishchenko2020-11-011-1/+2
* Adding an option to write Verilog with LUT instances (compiler warnings).Alan Mishchenko2020-10-312-3/+3
* Adding an option to write Verilog with LUT instances.Alan Mishchenko2020-10-312-3/+196
* Fixing a clang error related to 'unlink'.Alan Mishchenko2020-10-091-0/+3
* New command 'read_sf'.Alan Mishchenko2020-10-012-0/+128
* Ongoing changes to the simulator.Alan Mishchenko2020-03-091-0/+2
* Adding CNF variable mapping rules.Alan Mishchenko2020-01-181-0/+11
* Updates to JSON parser.Alan Mishchenko2019-12-021-0/+20
* Updates to JSON parser.Alan Mishchenko2019-12-022-7/+138
* Adding logfile dump to print_status.Alan Mishchenko2019-11-251-0/+26
* Dumping multiple counter-examples.Alan Mishchenko2019-11-191-1/+1
* Dumping multiple counter-examples.Alan Mishchenko2019-11-191-1/+1
* Dumping multiple counter-examples.Alan Mishchenko2019-11-191-104/+139
* Bug fix in parsing hierarchical BLIF with mapping.Alan Mishchenko2019-11-181-3/+16
* Fix read_bench to read standard gate names in lower-case.Alan Mishchenko2019-08-281-9/+9
* Adding synonym of 'read_dsd'.Alan Mishchenko2019-06-201-0/+1
* Modifying 'write_truth' to dump truth table in hex.Alan Mishchenko2019-05-071-3/+11
* Adding switch 'read_truth -f <file_name>' to read truth table from file.Alan Mishchenko2019-04-151-9/+22
* Fixing some warnings by adding cast from 'int' to 'size_t' in memset, memcpy,...Alan Mishchenko2019-03-053-4/+4
* Suggested white-space changes for fewer gcc warnings.Alan Mishchenko2019-03-041-1/+1
* Add skip feature to CEX printing.Alan Mishchenko2019-02-081-1/+9
* Exploring other ways of CEX writing.Alan Mishchenko2019-01-211-5/+51
* Undoing some recent changes for improved CEX writing.Alan Mishchenko2019-01-211-65/+8
* Fixing the problem with outputting word-level CEXes after retiming.Alan Mishchenko2019-01-181-12/+28
* Fixing the problem with outputting word-level CEXes after retiming.Alan Mishchenko2019-01-171-19/+37
* Fixing the problem with outputting word-level CEXes.Alan Mishchenko2019-01-161-1/+24
* Various usability changes.Alan Mishchenko2018-11-181-3/+14
* Adding switch to 'write_pla' to write random onset minterms of the first PO f...Alan Mishchenko2018-09-291-2/+8
* Adding switch to 'write_pla' to write random onset minterms of the first PO f...Alan Mishchenko2018-09-282-10/+154
* Adding switch 'clp -o' to reverse initial variable ordering.Alan Mishchenko2018-06-071-1/+1
* Integrating SAT-based CEX minimization (bug fix).Alan Mishchenko2018-03-251-2/+2
* Integrating SAT-based CEX minimization.Alan Mishchenko2018-03-251-8/+20
* Bug fix in 'write_aiger_cex'.Alan Mishchenko2017-12-201-0/+1
* Adding switch -a to 'write_verilog' to write factored forms without XORs and ...Alan Mishchenko2017-12-034-16/+29
* Fixing minimize_assuptions using Glucose.Alan Mishchenko2017-10-021-0/+1
* Maintenance and updates.Alan Mishchenko2017-09-241-1/+1
* Compiler warnings.Alan Mishchenko2017-07-221-2/+2
* Adding PDR with abstraction.Alan Mishchenko2017-02-101-1/+1
* Improving CEX minimization.Alan Mishchenko2017-02-101-1/+1
* Improvements in AIG visualization.Alan Mishchenko2017-02-051-2/+2
* Updates to arithmetic verification.Alan Mishchenko2017-01-301-1/+1
* Commenting out bailout in 'print_cex' when CEX has latches initialized to 1.Alan Mishchenko2016-11-301-1/+2
* New SAT-based optimization package.Alan Mishchenko2016-11-261-1/+1
* Parser for JSON format.Alan Mishchenko2016-10-254-2/+391
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