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* Merge remote-tracking branch 'upstream/master' into yosys-experimentalMiodrag Milanovic2022-07-042-19/+99
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| * Supporting new resub problem format.Alan Mishchenko2022-06-021-0/+53
| * Improving truth table handling.Alan Mishchenko2022-02-161-0/+10
| * Improving truth table handling.Alan Mishchenko2022-02-031-19/+24
| * Outputting the constant node in 'write_gml'.Alan Mishchenko2021-12-061-0/+12
* | read_cex: Allow reading cex that has extra registersJannis Harder2022-07-011-0/+6
* | distinquish between old and new format as wellMiodrag Milanovic2022-05-061-3/+3
* | Give more reasonable error on read_cex and handle statusMiodrag Milanovic2022-05-061-4/+7
* | Fix for unhandled aiw file commandsMiodrag Milanovic2022-04-151-2/+2
* | Make read_cex able to append if some latches are missingMiodrag Milanovic2022-04-131-3/+11
* | fix buffer errorMiodrag Milanovic2022-03-221-2/+5
* | gcc 4.8 fixMiodrag Milanovic2022-03-041-3/+3
* | read_cex (#12)Miodrag Milanović2022-03-041-7/+285
* | Fixes and more cleanups in write_cex output codeClaire Xenia Wolf2022-02-151-34/+27
* | Cleanups in write_cex output formatClaire Xenia Wolf2022-02-151-2/+7
* | Enable writing of minimized Cex in non-names modeClaire Xenia Wolf2022-02-151-3/+7
* | write_cex - add minimize using algorithm from cexinfo commandMiodrag Milanovic2021-11-191-4/+36
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* Various changes.Alan Mishchenko2021-09-021-0/+9
* Compiler warnings.Alan Mishchenko2021-08-231-1/+1
* Suggested changes to collect and pass timing information.Alan Mishchenko2021-08-121-5/+14
* Updating LUT synthesis code.Alan Mishchenko2021-05-162-16/+89
* Disable cube-sort when deriving SOPs.Alan Mishchenko2021-05-111-2/+2
* Updating LUT synthesis code.Alan Mishchenko2021-05-111-1/+1
* Making sure read_bench can read nodes up to 15 inputs.Alan Mishchenko2021-04-302-5/+6
* Passing node labels.Alan Mishchenko2021-04-261-0/+8
* Trying to explicitly compute don't-cares during optimization.Alan Mishchenko2020-11-011-1/+2
* Adding an option to write Verilog with LUT instances (compiler warnings).Alan Mishchenko2020-10-312-3/+3
* Adding an option to write Verilog with LUT instances.Alan Mishchenko2020-10-312-3/+196
* Fixing a clang error related to 'unlink'.Alan Mishchenko2020-10-091-0/+3
* New command 'read_sf'.Alan Mishchenko2020-10-012-0/+128
* Ongoing changes to the simulator.Alan Mishchenko2020-03-091-0/+2
* Adding CNF variable mapping rules.Alan Mishchenko2020-01-181-0/+11
* Updates to JSON parser.Alan Mishchenko2019-12-021-0/+20
* Updates to JSON parser.Alan Mishchenko2019-12-022-7/+138
* Adding logfile dump to print_status.Alan Mishchenko2019-11-251-0/+26
* Dumping multiple counter-examples.Alan Mishchenko2019-11-191-1/+1
* Dumping multiple counter-examples.Alan Mishchenko2019-11-191-1/+1
* Dumping multiple counter-examples.Alan Mishchenko2019-11-191-104/+139
* Bug fix in parsing hierarchical BLIF with mapping.Alan Mishchenko2019-11-181-3/+16
* Fix read_bench to read standard gate names in lower-case.Alan Mishchenko2019-08-281-9/+9
* Adding synonym of 'read_dsd'.Alan Mishchenko2019-06-201-0/+1
* Modifying 'write_truth' to dump truth table in hex.Alan Mishchenko2019-05-071-3/+11
* Adding switch 'read_truth -f <file_name>' to read truth table from file.Alan Mishchenko2019-04-151-9/+22
* Fixing some warnings by adding cast from 'int' to 'size_t' in memset, memcpy,...Alan Mishchenko2019-03-053-4/+4
* Suggested white-space changes for fewer gcc warnings.Alan Mishchenko2019-03-041-1/+1
* Add skip feature to CEX printing.Alan Mishchenko2019-02-081-1/+9
* Exploring other ways of CEX writing.Alan Mishchenko2019-01-211-5/+51
* Undoing some recent changes for improved CEX writing.Alan Mishchenko2019-01-211-65/+8
* Fixing the problem with outputting word-level CEXes after retiming.Alan Mishchenko2019-01-181-12/+28
* Fixing the problem with outputting word-level CEXes after retiming.Alan Mishchenko2019-01-171-19/+37
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