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* An add-on to write Verilog for circuits mapped into simple gates.Alan Mishchenko2016-02-011-9/+22
* Changing 'refactor' to work with truth tables.Alan Mishchenko2015-08-251-7/+0
* Changes to be able to compile ABC without CUDD.Alan Mishchenko2015-08-241-1/+1
* Changes to be able to compile ABC without CUDD.Alan Mishchenko2015-08-241-0/+7
* Changes to be able to compile ABC without CUDD.Alan Mishchenko2015-08-241-0/+10
* Improvements to Cba data-structure.Alan Mishchenko2015-07-291-4/+4
* Improvements to Cba data-structure.Alan Mishchenko2015-07-281-2/+2
* Several additional fixed in the timing manager.Alan Mishchenko2015-04-072-2/+14
* Improvements in reading timing information from BLIF.Alan Mishchenko2015-04-051-18/+127
* Properly copying and saving the timing info in &get and &put.Alan Mishchenko2015-04-041-20/+17
* Properly copying and saving the timing info in &get and &put.Alan Mishchenko2015-04-042-5/+6
* Adding switch '-b' in 'read_pla'.Alan Mishchenko2015-03-184-16/+31
* Propagating changes after updating flag of 'sop'.Alan Mishchenko2015-02-194-8/+8
* Adding resource limit switch -C to 'sop'.Alan Mishchenko2015-02-114-9/+9
* Fixed a typo in variable names.Alan Mishchenko2015-02-076-11/+11
* Improvements and tuning of CBA with buffering/sizing.Alan Mishchenko2015-02-041-3/+12
* Esperiments with MO PLA optimization.Alan Mishchenko2015-02-034-43/+303
* Preprocessing for multi-output PLA tables.Alan Mishchenko2015-01-311-3/+1
* Preprocessing for multi-output PLA tables.Alan Mishchenko2015-01-311-19/+93
* Preprocessing for multi-output PLA tables.Alan Mishchenko2015-01-311-22/+93
* Preprocessing for multi-output PLA tables.Alan Mishchenko2015-01-311-45/+61
* Preprocessing for multi-output PLA tables.Alan Mishchenko2015-01-311-0/+124
* Integrating barrier buffers.Alan Mishchenko2014-12-131-2/+1
* Generation of barrier-buffers for hierarchical design.Alan Mishchenko2014-11-112-7/+10
* Adding cyclicity check for netlist with boxes.Alan Mishchenko2014-11-102-3/+34
* Deriving AIG after cell mapping.Alan Mishchenko2014-10-031-1/+1
* Adding out-of-bounds checks to AIGER readers.Alan Mishchenko2014-09-281-1/+1
* Adding features to CNF generation.Alan Mishchenko2014-09-281-6/+16
* New word-level representation package.Alan Mishchenko2014-09-121-57/+0
* Bug fix in transferring timing info.Alan Mishchenko2014-09-091-0/+57
* Compiler warning.Alan Mishchenko2014-08-271-2/+2
* Improvements BLIF parser.Alan Mishchenko2014-08-271-0/+126
* Improvements to power-aware mapping.Alan Mishchenko2014-06-231-1/+1
* Improvements to CNF generation.Alan Mishchenko2014-06-231-1/+1
* Improvements to CNF generation.Alan Mishchenko2014-06-231-9/+35
* Added quick GIG parser.Alan Mishchenko2014-06-191-0/+59
* Bug fix in writing latch init values in 'write_aiger'.Alan Mishchenko2014-06-171-3/+3
* Fix PLA reader to correctly report error file numbers.Alan Mishchenko2014-06-021-5/+6
* add an option to write_cex to write the CEX in AIGER 1.9 format.Baruch Sterin2014-05-121-1/+11
* Added dumping original object names into a file.Alan Mishchenko2014-04-261-2/+12
* Renamed Abc_Lib_t into Abc_Des_t and removed some dead code.Alan Mishchenko2014-04-093-249/+17
* Better CEX minimization and renaming of write_counter into write_cex.Alan Mishchenko2014-04-041-12/+27
* Adding functionally observable fault testing.Alan Mishchenko2014-03-311-2/+5
* Improving network visualization in show/&show.Alan Mishchenko2014-03-281-2/+26
* Adding barrier buffers.Alan Mishchenko2014-03-183-11/+33
* Adding barrier buffers.Alan Mishchenko2014-03-163-21/+51
* Changes to LUT mappers.Alan Mishchenko2014-03-091-0/+4
* Adding check for the presence of precomputed data.Alan Mishchenko2013-12-291-0/+5
* New command &write_cnf.Alan Mishchenko2013-12-181-0/+66
* Bug fixes in the above patches.Alan Mishchenko2013-12-031-4/+4
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