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yosys-experimental
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Author
Age
Files
Lines
*
New MFS package.
Alan Mishchenko
2013-05-24
1
-4
/
+4
*
Commenting assertion that does not hold in AIGER 1.9, accoring to Baruch Sterin.
Alan Mishchenko
2013-05-13
1
-1
/
+1
*
Enabled 'cec' to be applied to networks derived from BLIF with EXDCs.
Alan Mishchenko
2013-04-18
1
-3
/
+4
*
Enabled reading the EXDC network by the default BLIF reader.
Alan Mishchenko
2013-04-18
2
-5
/
+29
*
Fixing both AIGER readers (read_aiger and &r) to work with AIGER 1.9 (except ...
Alan Mishchenko
2013-04-18
1
-2
/
+8
*
Fixing both AIGER readers (read_aiger and &r) to work with AIGER 1.9 (except ...
Alan Mishchenko
2013-04-17
1
-4
/
+4
*
Bug fix in 'write_pla'.
Alan Mishchenko
2013-04-15
1
-1
/
+1
*
Improvements to the hierarchy/timing manager.
Alan Mishchenko
2013-03-05
1
-0
/
+2
*
Fixing compilation problems on Linux-32 related to constants of type unsigned...
Alan Mishchenko
2013-01-30
1
-12
/
+12
*
Fixing C++ compilation issues.
Alan Mishchenko
2013-01-08
1
-0
/
+3
*
Improvements to LMS code.
Alan Mishchenko
2012-11-06
1
-2
/
+2
*
Adding binary file dumping for truth tables.
Alan Mishchenko
2012-10-25
1
-1
/
+1
*
Adding binary file dumping for truth tables.
Alan Mishchenko
2012-10-25
1
-4
/
+18
*
Added hierarchical BLIF output for mapping with LUT structures (write_blif -a...
Alan Mishchenko
2012-10-24
3
-15
/
+296
*
Bug fix in hierarchical BLIF reader.
Alan Mishchenko
2012-10-11
1
-3
/
+2
*
Added command to transform GIA into the file with truth tables for each output.
Alan Mishchenko
2012-10-10
1
-0
/
+77
*
Making explicit cast to 64-bit unsigned in a few places.
Alan Mishchenko
2012-10-09
1
-1
/
+1
*
C++ portability changes.
Alan Mishchenko
2012-10-03
1
-1
/
+1
*
Replacing 'st_table' by 'st__table' to resolve linker problems.
Alan Mishchenko
2012-09-29
1
-1
/
+1
*
Cleaned up interfaces of genlib/liberty/supergate reading/writing.
Alan Mishchenko
2012-09-25
1
-5
/
+18
*
Changed printouts in a few places in supergate computation.
Alan Mishchenko
2012-09-24
1
-0
/
+2
*
Added simplification before the concurrent call to PDR.
Alan Mishchenko
2012-09-20
1
-2
/
+2
*
Modified 'read' to read all types of libraries (genlib, liberty, scl).
Alan Mishchenko
2012-09-20
1
-0
/
+2
*
Modified 'read' to read all types of libraries (genlib, liberty, scl).
Alan Mishchenko
2012-09-20
2
-2
/
+17
*
Fixes to Verilog parser.
Alan Mishchenko
2012-09-20
1
-0
/
+6
*
Extending Liberty parser to handle multi-output cells.
Alan Mishchenko
2012-09-19
1
-6
/
+6
*
Extending Liberty parser to handle multi-output cells.
Alan Mishchenko
2012-09-19
1
-18
/
+7
*
Extending BLIF parser/write to hangle multi-output cells.
Alan Mishchenko
2012-09-19
3
-93
/
+210
*
Created new abstraction package from the code that was all over the place.
Alan Mishchenko
2012-09-15
1
-0
/
+1
*
Scalable gate-level abstraction.
Alan Mishchenko
2012-09-11
1
-9
/
+30
*
Fixing Verilog writer's way of writing module names.
Alan Mishchenko
2012-09-11
1
-1
/
+1
*
Fixing the way constants are written into mapped Verilog files.
Alan Mishchenko
2012-08-31
1
-0
/
+5
*
Updating project settings to have simpler include paths.
Alan Mishchenko
2012-07-07
17
-37
/
+37
*
Fixing time primtouts throughout the code.
Alan Mishchenko
2012-07-07
1
-1
/
+2
*
Fixing time primtouts throughout the code.
Alan Mishchenko
2012-07-07
3
-5
/
+3
*
Diabling compact AIGER writing by default.
Alan Mishchenko
2012-07-07
1
-1
/
+1
*
Improving printouts of critical path.
Alan Mishchenko
2012-04-09
1
-2
/
+4
*
Silencing a gcc warning.
Alan Mishchenko
2012-03-23
1
-1
/
+1
*
Additional features for delay optimization
Alan Mishchenko
2012-03-21
2
-0
/
+44
*
Renamed Aig_ObjIsPi/Po to be ...Ci/Co and Aig_Man(Pi/Po)Num to be ...(Ci/Co)...
Alan Mishchenko
2012-03-09
1
-1
/
+1
*
Renamed Aig_ManForEachPi/Po to be ...Ci/Co and Aig_ObjCreatePi/Po to be ...Ci...
Alan Mishchenko
2012-03-09
1
-1
/
+1
*
Enabling user-specified required times in 'map'.
Alan Mishchenko
2012-03-02
2
-2
/
+106
*
Silencing some of the gcc warnings.
Alan Mishchenko
2012-02-16
2
-5
/
+9
*
Silencing some of the gcc warnings.
Alan Mishchenko
2012-02-16
4
-6
/
+17
*
Graph isomorphism checking code.
Alan Mishchenko
2012-02-11
4
-11
/
+46
*
Major restructuring of the code.
Alan Mishchenko
2012-01-21
20
-51
/
+51
*
Added switch 'write_counter -f' to output flop values in each time frame.
Alan Mishchenko
2012-01-18
1
-20
/
+31
*
Bug fixes in the Verilog parser.
Alan Mishchenko
2012-01-14
1
-4
/
+10
*
New hierarchy manager.
Alan Mishchenko
2012-01-13
1
-1
/
+1
*
Added warning when the network from file has no primary inputs.
Alan Mishchenko
2012-01-06
1
-0
/
+5
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