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* Adding switch '-b' in 'read_pla'.Alan Mishchenko2015-03-184-16/+31
* Propagating changes after updating flag of 'sop'.Alan Mishchenko2015-02-194-8/+8
* Adding resource limit switch -C to 'sop'.Alan Mishchenko2015-02-114-9/+9
* Fixed a typo in variable names.Alan Mishchenko2015-02-076-11/+11
* Improvements and tuning of CBA with buffering/sizing.Alan Mishchenko2015-02-041-3/+12
* Esperiments with MO PLA optimization.Alan Mishchenko2015-02-034-43/+303
* Preprocessing for multi-output PLA tables.Alan Mishchenko2015-01-311-3/+1
* Preprocessing for multi-output PLA tables.Alan Mishchenko2015-01-311-19/+93
* Preprocessing for multi-output PLA tables.Alan Mishchenko2015-01-311-22/+93
* Preprocessing for multi-output PLA tables.Alan Mishchenko2015-01-311-45/+61
* Preprocessing for multi-output PLA tables.Alan Mishchenko2015-01-311-0/+124
* Integrating barrier buffers.Alan Mishchenko2014-12-131-2/+1
* Generation of barrier-buffers for hierarchical design.Alan Mishchenko2014-11-112-7/+10
* Adding cyclicity check for netlist with boxes.Alan Mishchenko2014-11-102-3/+34
* Deriving AIG after cell mapping.Alan Mishchenko2014-10-031-1/+1
* Adding out-of-bounds checks to AIGER readers.Alan Mishchenko2014-09-281-1/+1
* Adding features to CNF generation.Alan Mishchenko2014-09-281-6/+16
* New word-level representation package.Alan Mishchenko2014-09-121-57/+0
* Bug fix in transferring timing info.Alan Mishchenko2014-09-091-0/+57
* Compiler warning.Alan Mishchenko2014-08-271-2/+2
* Improvements BLIF parser.Alan Mishchenko2014-08-271-0/+126
* Improvements to power-aware mapping.Alan Mishchenko2014-06-231-1/+1
* Improvements to CNF generation.Alan Mishchenko2014-06-231-1/+1
* Improvements to CNF generation.Alan Mishchenko2014-06-231-9/+35
* Added quick GIG parser.Alan Mishchenko2014-06-191-0/+59
* Bug fix in writing latch init values in 'write_aiger'.Alan Mishchenko2014-06-171-3/+3
* Fix PLA reader to correctly report error file numbers.Alan Mishchenko2014-06-021-5/+6
* add an option to write_cex to write the CEX in AIGER 1.9 format.Baruch Sterin2014-05-121-1/+11
* Added dumping original object names into a file.Alan Mishchenko2014-04-261-2/+12
* Renamed Abc_Lib_t into Abc_Des_t and removed some dead code.Alan Mishchenko2014-04-093-249/+17
* Better CEX minimization and renaming of write_counter into write_cex.Alan Mishchenko2014-04-041-12/+27
* Adding functionally observable fault testing.Alan Mishchenko2014-03-311-2/+5
* Improving network visualization in show/&show.Alan Mishchenko2014-03-281-2/+26
* Adding barrier buffers.Alan Mishchenko2014-03-183-11/+33
* Adding barrier buffers.Alan Mishchenko2014-03-163-21/+51
* Changes to LUT mappers.Alan Mishchenko2014-03-091-0/+4
* Adding check for the presence of precomputed data.Alan Mishchenko2013-12-291-0/+5
* New command &write_cnf.Alan Mishchenko2013-12-181-0/+66
* Bug fixes in the above patches.Alan Mishchenko2013-12-031-4/+4
* Suggested patch of AIG writers.Alan Mishchenko2013-12-031-30/+106
* Bug fix in writing constants in write_verilog.Alan Mishchenko2013-11-211-1/+1
* Compiler warnings.Alan Mishchenko2013-10-171-4/+8
* Debugging and finetuning the flow.Alan Mishchenko2013-09-172-1/+3
* Unifying standard cell library representations.Alan Mishchenko2013-09-171-1/+1
* Adding switch 'ps -s' to skip counting buffers/inverters as nodes.Alan Mishchenko2013-09-021-2/+0
* Removing some old useless code.Alan Mishchenko2013-09-021-4/+0
* Removing some old useless code.Alan Mishchenko2013-09-022-257/+2
* Adding support for input slew and output capacitance to timer and gate-sizer ...Alan Mishchenko2013-07-241-2/+20
* Tuning standard-cell mapping flow.Alan Mishchenko2013-07-231-1/+1
* Improvements to post-mapping re-sizing.Alan Mishchenko2013-07-211-14/+16
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