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* Adding a wrapper around clock() for more accurate time counting in ABC.Alan Mishchenko2013-05-271-18/+18
* New MFS package.Alan Mishchenko2013-05-241-4/+4
* Commenting assertion that does not hold in AIGER 1.9, accoring to Baruch Sterin.Alan Mishchenko2013-05-131-1/+1
* Enabled 'cec' to be applied to networks derived from BLIF with EXDCs.Alan Mishchenko2013-04-181-3/+4
* Enabled reading the EXDC network by the default BLIF reader.Alan Mishchenko2013-04-182-5/+29
* Fixing both AIGER readers (read_aiger and &r) to work with AIGER 1.9 (except ...Alan Mishchenko2013-04-181-2/+8
* Fixing both AIGER readers (read_aiger and &r) to work with AIGER 1.9 (except ...Alan Mishchenko2013-04-171-4/+4
* Bug fix in 'write_pla'.Alan Mishchenko2013-04-151-1/+1
* Improvements to the hierarchy/timing manager.Alan Mishchenko2013-03-051-0/+2
* Fixing compilation problems on Linux-32 related to constants of type unsigned...Alan Mishchenko2013-01-301-12/+12
* Fixing C++ compilation issues.Alan Mishchenko2013-01-081-0/+3
* Improvements to LMS code.Alan Mishchenko2012-11-061-2/+2
* Adding binary file dumping for truth tables.Alan Mishchenko2012-10-251-1/+1
* Adding binary file dumping for truth tables.Alan Mishchenko2012-10-251-4/+18
* Added hierarchical BLIF output for mapping with LUT structures (write_blif -a...Alan Mishchenko2012-10-243-15/+296
* Bug fix in hierarchical BLIF reader.Alan Mishchenko2012-10-111-3/+2
* Added command to transform GIA into the file with truth tables for each output.Alan Mishchenko2012-10-101-0/+77
* Making explicit cast to 64-bit unsigned in a few places.Alan Mishchenko2012-10-091-1/+1
* C++ portability changes.Alan Mishchenko2012-10-031-1/+1
* Replacing 'st_table' by 'st__table' to resolve linker problems.Alan Mishchenko2012-09-291-1/+1
* Cleaned up interfaces of genlib/liberty/supergate reading/writing.Alan Mishchenko2012-09-251-5/+18
* Changed printouts in a few places in supergate computation.Alan Mishchenko2012-09-241-0/+2
* Added simplification before the concurrent call to PDR.Alan Mishchenko2012-09-201-2/+2
* Modified 'read' to read all types of libraries (genlib, liberty, scl).Alan Mishchenko2012-09-201-0/+2
* Modified 'read' to read all types of libraries (genlib, liberty, scl).Alan Mishchenko2012-09-202-2/+17
* Fixes to Verilog parser.Alan Mishchenko2012-09-201-0/+6
* Extending Liberty parser to handle multi-output cells.Alan Mishchenko2012-09-191-6/+6
* Extending Liberty parser to handle multi-output cells.Alan Mishchenko2012-09-191-18/+7
* Extending BLIF parser/write to hangle multi-output cells.Alan Mishchenko2012-09-193-93/+210
* Created new abstraction package from the code that was all over the place.Alan Mishchenko2012-09-151-0/+1
* Scalable gate-level abstraction.Alan Mishchenko2012-09-111-9/+30
* Fixing Verilog writer's way of writing module names.Alan Mishchenko2012-09-111-1/+1
* Fixing the way constants are written into mapped Verilog files.Alan Mishchenko2012-08-311-0/+5
* Updating project settings to have simpler include paths.Alan Mishchenko2012-07-0717-37/+37
* Fixing time primtouts throughout the code.Alan Mishchenko2012-07-071-1/+2
* Fixing time primtouts throughout the code.Alan Mishchenko2012-07-073-5/+3
* Diabling compact AIGER writing by default.Alan Mishchenko2012-07-071-1/+1
* Improving printouts of critical path.Alan Mishchenko2012-04-091-2/+4
* Silencing a gcc warning.Alan Mishchenko2012-03-231-1/+1
* Additional features for delay optimizationAlan Mishchenko2012-03-212-0/+44
* Renamed Aig_ObjIsPi/Po to be ...Ci/Co and Aig_Man(Pi/Po)Num to be ...(Ci/Co)...Alan Mishchenko2012-03-091-1/+1
* Renamed Aig_ManForEachPi/Po to be ...Ci/Co and Aig_ObjCreatePi/Po to be ...Ci...Alan Mishchenko2012-03-091-1/+1
* Enabling user-specified required times in 'map'.Alan Mishchenko2012-03-022-2/+106
* Silencing some of the gcc warnings.Alan Mishchenko2012-02-162-5/+9
* Silencing some of the gcc warnings.Alan Mishchenko2012-02-164-6/+17
* Graph isomorphism checking code.Alan Mishchenko2012-02-114-11/+46
* Major restructuring of the code.Alan Mishchenko2012-01-2120-51/+51
* Added switch 'write_counter -f' to output flop values in each time frame.Alan Mishchenko2012-01-181-20/+31
* Bug fixes in the Verilog parser.Alan Mishchenko2012-01-141-4/+10
* New hierarchy manager.Alan Mishchenko2012-01-131-1/+1
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