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path: root/src/base/wlc/wlc.h
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* %pdra -L: now applies to all typesYen-Sheng Ho2017-02-271-1/+1
* added an option -L to %pdra for limiting the number of muxesYen-Sheng Ho2017-02-261-0/+1
* added an option -b to %pdraYen-Sheng Ho2017-02-251-0/+2
* added %pdra -a: run with pdr -nctYen-Sheng Ho2017-02-231-0/+1
* added an option -m for %pdraYen-Sheng Ho2017-02-221-0/+1
* clean upYen-Sheng Ho2017-02-211-17/+1
* added options of checking and pushing to %pdraYen-Sheng Ho2017-02-201-0/+2
* added datastructure for %pdra optionsYen-Sheng Ho2017-02-201-1/+17
* working on pdr with wlaYen-Sheng Ho2017-02-191-0/+1
* Word-level abstraction engine.Alan Mishchenko2017-02-151-8/+17
* Word-level abstraction.Alan Mishchenko2017-02-091-1/+2
* Word-level abstraction.Alan Mishchenko2017-02-091-1/+14
* Adding visualization of word-level networks Wlc_Ntk_t.Alan Mishchenko2017-01-261-1/+1
* Adding visualization of word-level networks Wlc_Ntk_t.Alan Mishchenko2017-01-261-4/+9
* Adding visualization of word-level networks Wlc_Ntk_t.Alan Mishchenko2017-01-261-1/+11
* Improvements to SMT-LIB parser.Alan Mishchenko2017-01-261-0/+1
* New command to profile arithmetic logic cones.Alan Mishchenko2016-11-261-0/+6
* Change Verilog reader to take a string rather than file name.Alan Mishchenko2016-10-061-1/+1
* Updates to arithmetic verification.Alan Mishchenko2016-08-051-1/+1
* Adding output range support to %blast.Alan Mishchenko2016-07-181-1/+1
* Changes to Wlc to accommodate signed signals in SMT-LIB.Alan Mishchenko2016-06-071-0/+2
* New profiling features for word-level optimizations.Alan Mishchenko2016-06-041-1/+1
* Improving SMT-LIB parser.Alan Mishchenko2016-05-231-8/+10
* Improving SMT-LIB parser.Alan Mishchenko2016-05-211-36/+37
* Improving SMT-LIB parser.Alan Mishchenko2016-05-201-0/+2
* Enabling AIGs without structural hashing.Alan Mishchenko2016-05-201-1/+1
* Experiments with CEC for arithmetic circuits.Alan Mishchenko2016-05-071-0/+1
* Supporting negative and reverse ranges of word-level variables in Wlc.Alan Mishchenko2016-04-041-38/+40
* Supporting bit-wise XNOR operator in Wlc_Ntk_t.Alan Mishchenko2016-03-181-0/+1
* Supporting complemented reduction operators.Alan Mishchenko2016-03-101-0/+3
* Adding support for a different bit-blasting of a multiplier and squarer.Alan Mishchenko2016-02-121-2/+3
* Supporting X-valued constants in Wlc_Ntk_t.Alan Mishchenko2016-02-021-0/+1
* Improving Wlc_Ntk_t data-structure by extending bit-ranges up to 4B enabling ...Alan Mishchenko2015-07-161-4/+4
* Improved bit-blasting of various operators in Wlc_Ntk_t; added SQRT operator ...Alan Mishchenko2015-07-141-2/+4
* Bug fixing in %blast when blasting MUX coming from always-statement.Alan Mishchenko2015-07-071-1/+1
* Bug fixing in %blast when blasting mod operator (handling zero divisor).Alan Mishchenko2015-07-071-1/+1
* Adding new debugging feature to Wlc_Ntk_t.Alan Mishchenko2015-06-191-0/+1
* Sequential word-level simulator for Wlc_Ntk_t.Alan Mishchenko2015-06-041-0/+4
* Fix inconsistency between operators and symbols in Wlc_Ntk_t.Alan Mishchenko2015-04-251-19/+19
* Modifications to read SMTLIB file from stdin.Alan Mishchenko2015-02-181-3/+2
* Modifications to read SMTLIB file from stdin.Alan Mishchenko2015-02-151-18/+21
* Modifications to read SMTLIB file from stdin.Alan Mishchenko2015-02-111-0/+6
* Added SMT parser for Wlc_Ntk_t.Alan Mishchenko2015-02-071-2/+4
* Outputting initial state in Wlc_Ntk_t.Alan Mishchenko2015-01-251-1/+1
* Support of init-state in AIGs derived from word-level designs in Wlc_Ntk_t.Alan Mishchenko2015-01-211-0/+2
* Improvements to word-level network package.Alan Mishchenko2014-11-141-56/+63
* Enabling AIGs with boxes for word-level and sequential designs.Alan Mishchenko2014-11-131-1/+4
* Support for sequential designs in word-level Verilog.Alan Mishchenko2014-09-261-7/+25
* Enabling print-out, for each operator, of the percetage of AND nodes after bi...Alan Mishchenko2014-09-251-1/+2
* Printing node type statistics.Alan Mishchenko2014-09-241-0/+2
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