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iCE40/abc
yosys-experimental
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wlc
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wlc.h
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Author
Age
Files
Lines
*
Outputting initial state in Wlc_Ntk_t.
Alan Mishchenko
2015-01-25
1
-1
/
+1
*
Support of init-state in AIGs derived from word-level designs in Wlc_Ntk_t.
Alan Mishchenko
2015-01-21
1
-0
/
+2
*
Improvements to word-level network package.
Alan Mishchenko
2014-11-14
1
-56
/
+63
*
Enabling AIGs with boxes for word-level and sequential designs.
Alan Mishchenko
2014-11-13
1
-1
/
+4
*
Support for sequential designs in word-level Verilog.
Alan Mishchenko
2014-09-26
1
-7
/
+25
*
Enabling print-out, for each operator, of the percetage of AND nodes after bi...
Alan Mishchenko
2014-09-25
1
-1
/
+2
*
Printing node type statistics.
Alan Mishchenko
2014-09-24
1
-0
/
+2
*
Improvements to word-level Verilog parser.
Alan Mishchenko
2014-09-17
1
-69
/
+72
*
Improvements to word-level Verilog parser.
Alan Mishchenko
2014-09-16
1
-1
/
+5
*
Compiler error (duplicate typedef).
Alan Mishchenko
2014-09-15
1
-1
/
+0
*
Compiler warnings.
Alan Mishchenko
2014-09-12
1
-45
/
+1
*
New word-level representation package.
Alan Mishchenko
2014-09-12
1
-0
/
+273