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path: root/src/base/wlc/wlcBlast.c
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* Support of init-state in AIGs derived from word-level designs in Wlc_Ntk_t.Alan Mishchenko2015-01-211-1/+1
* Support of init-state in AIGs derived from word-level designs in Wlc_Ntk_t.Alan Mishchenko2015-01-211-0/+14
* Integrating barrier buffers.Alan Mishchenko2014-12-081-1/+1
* Added and verified bit-blasting of power operator.Alan Mishchenko2014-11-301-0/+32
* Improvements to word-level network package.Alan Mishchenko2014-11-141-16/+16
* Enabling AIGs with boxes for word-level and sequential designs.Alan Mishchenko2014-11-141-4/+5
* Enabling AIGs with boxes for word-level and sequential designs.Alan Mishchenko2014-11-131-10/+106
* Bug fix in blasting MUX with different ranges of inputs and the output.Alan Mishchenko2014-11-101-2/+2
* Bug fix in the bit-blaster.Alan Mishchenko2014-10-101-3/+3
* Improvements to bit-blaster.Alan Mishchenko2014-10-011-14/+42
* Improvements to bit-blaster.Alan Mishchenko2014-09-301-1/+1
* Improvements to bit-blaster.Alan Mishchenko2014-09-301-72/+111
* Support for sequential designs in word-level Verilog.Alan Mishchenko2014-09-261-14/+23
* Enabling print-out, for each operator, of the percetage of AND nodes after bi...Alan Mishchenko2014-09-251-0/+6
* Added support of word-level MUXes represented as 'always'-statements.Alan Mishchenko2014-09-241-2/+2
* Added support of word-level MUXes represented as 'always'-statements.Alan Mishchenko2014-09-241-16/+48
* Debugging the bit-blaster.Alan Mishchenko2014-09-231-1/+15
* Debugging the bit-blaster.Alan Mishchenko2014-09-231-7/+27
* Improvements to word-level Verilog parser.Alan Mishchenko2014-09-171-119/+282
* Improvements to word-level Verilog parser.Alan Mishchenko2014-09-161-0/+6
* Compiler warnings.Alan Mishchenko2014-09-121-1/+1
* New word-level representation package.Alan Mishchenko2014-09-121-0/+363