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iCE40/abc
yosys-experimental
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wlc
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wlcBlast.c
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Author
Age
Files
Lines
...
*
Enabling AIGs with boxes for word-level and sequential designs.
Alan Mishchenko
2014-11-13
1
-10
/
+106
*
Bug fix in blasting MUX with different ranges of inputs and the output.
Alan Mishchenko
2014-11-10
1
-2
/
+2
*
Bug fix in the bit-blaster.
Alan Mishchenko
2014-10-10
1
-3
/
+3
*
Improvements to bit-blaster.
Alan Mishchenko
2014-10-01
1
-14
/
+42
*
Improvements to bit-blaster.
Alan Mishchenko
2014-09-30
1
-1
/
+1
*
Improvements to bit-blaster.
Alan Mishchenko
2014-09-30
1
-72
/
+111
*
Support for sequential designs in word-level Verilog.
Alan Mishchenko
2014-09-26
1
-14
/
+23
*
Enabling print-out, for each operator, of the percetage of AND nodes after bi...
Alan Mishchenko
2014-09-25
1
-0
/
+6
*
Added support of word-level MUXes represented as 'always'-statements.
Alan Mishchenko
2014-09-24
1
-2
/
+2
*
Added support of word-level MUXes represented as 'always'-statements.
Alan Mishchenko
2014-09-24
1
-16
/
+48
*
Debugging the bit-blaster.
Alan Mishchenko
2014-09-23
1
-1
/
+15
*
Debugging the bit-blaster.
Alan Mishchenko
2014-09-23
1
-7
/
+27
*
Improvements to word-level Verilog parser.
Alan Mishchenko
2014-09-17
1
-119
/
+282
*
Improvements to word-level Verilog parser.
Alan Mishchenko
2014-09-16
1
-0
/
+6
*
Compiler warnings.
Alan Mishchenko
2014-09-12
1
-1
/
+1
*
New word-level representation package.
Alan Mishchenko
2014-09-12
1
-0
/
+363
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