index
:
iCE40/abc
yosys-experimental
[no description]
summary
refs
log
tree
commit
diff
stats
log msg
author
committer
range
path:
root
/
src
/
base
/
wlc
/
wlcNtk.c
Commit message (
Collapse
)
Author
Age
Files
Lines
*
Experiments with CEC for arithmetic circuits.
Alan Mishchenko
2016-05-07
1
-0
/
+5
|
*
Supporting negative and reverse ranges of word-level variables in Wlc.
Alan Mishchenko
2016-04-04
1
-39
/
+44
|
*
Typo in operator in Wlc_Ntk_t.
Alan Mishchenko
2016-03-18
1
-1
/
+1
|
*
Supporting bit-wise XNOR operator in Wlc_Ntk_t.
Alan Mishchenko
2016-03-18
1
-0
/
+3
|
*
Supporting complemented reduction operators.
Alan Mishchenko
2016-03-10
1
-0
/
+9
|
*
Adding support for a different bit-blasting of a multiplier and squarer.
Alan Mishchenko
2016-02-12
1
-0
/
+2
|
*
Supporting X-valued constants in Wlc_Ntk_t.
Alan Mishchenko
2016-02-02
1
-0
/
+1
|
*
Changes to be able to compile ABC without CUDD.
Alan Mishchenko
2015-08-24
1
-0
/
+1
|
*
Improving Wlc_Ntk_t data-structure by extending bit-ranges up to 4B enabling ↵
Alan Mishchenko
2015-07-16
1
-7
/
+92
|
|
|
|
printout of AND2 in '%ps -d'.
*
Improved bit-blasting of various operators in Wlc_Ntk_t; added SQRT operator ↵
Alan Mishchenko
2015-07-14
1
-2
/
+4
|
|
|
|
(@).
*
Bug fixing in %blast when blasting mod operator (handling zero divisor).
Alan Mishchenko
2015-07-07
1
-0
/
+2
|
*
Adding new debugging feature to Wlc_Ntk_t.
Alan Mishchenko
2015-06-19
1
-0
/
+53
|
*
Sequential word-level simulator for Wlc_Ntk_t.
Alan Mishchenko
2015-06-04
1
-0
/
+1
|
*
Fix inconsistency between operators and symbols in Wlc_Ntk_t.
Alan Mishchenko
2015-04-25
1
-18
/
+19
|
*
Modifications to read SMTLIB file from stdin.
Alan Mishchenko
2015-02-18
1
-46
/
+0
|
*
Modifications to read SMTLIB file from stdin.
Alan Mishchenko
2015-02-15
1
-0
/
+47
|
*
Modifications to read SMTLIB file from stdin.
Alan Mishchenko
2015-02-11
1
-1
/
+1
|
*
Added SMT parser for Wlc_Ntk_t.
Alan Mishchenko
2015-02-07
1
-0
/
+2
|
*
Outputting initial state in Wlc_Ntk_t.
Alan Mishchenko
2015-01-25
1
-1
/
+2
|
*
Support of init-state in AIGs derived from word-level designs in Wlc_Ntk_t.
Alan Mishchenko
2015-01-21
1
-1
/
+4
|
*
Improvements to word-level network package.
Alan Mishchenko
2014-11-14
1
-2
/
+2
|
*
Improvements to word-level network package.
Alan Mishchenko
2014-11-14
1
-31
/
+24
|
*
Enabling AIGs with boxes for word-level and sequential designs.
Alan Mishchenko
2014-11-13
1
-0
/
+24
|
*
Improvements to bit-blaster.
Alan Mishchenko
2014-09-30
1
-1
/
+6
|
*
Support for sequential designs in word-level Verilog.
Alan Mishchenko
2014-09-26
1
-28
/
+33
|
*
Enabling print-out, for each operator, of the percetage of AND nodes after ↵
Alan Mishchenko
2014-09-25
1
-10
/
+19
|
|
|
|
bit-blasting.
*
Printing node type statistics.
Alan Mishchenko
2014-09-24
1
-33
/
+57
|
*
Printing node type statistics.
Alan Mishchenko
2014-09-24
1
-10
/
+10
|
*
Printing node type statistics.
Alan Mishchenko
2014-09-24
1
-2
/
+104
|
*
Improvements to word-level Verilog parser.
Alan Mishchenko
2014-09-17
1
-28
/
+31
|
*
Improvements to word-level Verilog parser.
Alan Mishchenko
2014-09-16
1
-4
/
+11
|
*
Compiler warnings.
Alan Mishchenko
2014-09-12
1
-0
/
+44
|
*
New word-level representation package.
Alan Mishchenko
2014-09-12
1
-0
/
+283