| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Support for sequential designs in word-level Verilog. | Alan Mishchenko | 2014-09-26 | 1 | -28/+33 |
| * | Enabling print-out, for each operator, of the percetage of AND nodes after bi... | Alan Mishchenko | 2014-09-25 | 1 | -10/+19 |
| * | Printing node type statistics. | Alan Mishchenko | 2014-09-24 | 1 | -33/+57 |
| * | Printing node type statistics. | Alan Mishchenko | 2014-09-24 | 1 | -10/+10 |
| * | Printing node type statistics. | Alan Mishchenko | 2014-09-24 | 1 | -2/+104 |
| * | Improvements to word-level Verilog parser. | Alan Mishchenko | 2014-09-17 | 1 | -28/+31 |
| * | Improvements to word-level Verilog parser. | Alan Mishchenko | 2014-09-16 | 1 | -4/+11 |
| * | Compiler warnings. | Alan Mishchenko | 2014-09-12 | 1 | -0/+44 |
| * | New word-level representation package. | Alan Mishchenko | 2014-09-12 | 1 | -0/+283 |
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index : iCE40/abc | |
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