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path: root/src/base/wlc/wlcReadVer.c
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* Experiments with CEC for arithmetic circuits.Alan Mishchenko2016-05-071-0/+1
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* Supporting negative and reverse ranges of word-level variables in Wlc.Alan Mishchenko2016-04-041-19/+46
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* Supporting bit-wise XNOR operator in Wlc_Ntk_t.Alan Mishchenko2016-03-181-1/+1
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* Supporting complemented reduction operators.Alan Mishchenko2016-03-111-6/+7
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* Supporting complemented reduction operators.Alan Mishchenko2016-03-101-4/+14
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* Supporting ~^ as equality operator in Wlc.Alan Mishchenko2016-03-041-2/+3
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* Improving bit-blasting of a multiplier and squarer.Alan Mishchenko2016-02-131-1/+1
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* Adding support for a different bit-blasting of a multiplier and squarer.Alan Mishchenko2016-02-121-0/+2
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* Supporting X-valued constants in Wlc_Ntk_t.Alan Mishchenko2016-02-021-11/+16
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* Adding code to support gate profiles.Alan Mishchenko2015-12-141-1/+4
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* Extending Verilog parser to handle 'default' in the case-statement.Alan Mishchenko2015-12-071-11/+27
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* Making ABC error out instead of crashing when non-standard range is given.Alan Mishchenko2015-08-031-3/+8
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* Improving Wlc_Ntk_t data-structure by extending bit-ranges up to 4B enabling ↵Alan Mishchenko2015-07-161-1/+17
| | | | printout of AND2 in '%ps -d'.
* Improved bit-blasting of various operators in Wlc_Ntk_t; added SQRT operator ↵Alan Mishchenko2015-07-141-1/+3
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* Bug fixing in %blast when blasting MUX coming from always-statement.Alan Mishchenko2015-07-071-1/+3
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* Bug fixing in %blast when blasting mod operator (handling zero divisor).Alan Mishchenko2015-07-071-1/+1
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* Add warnings to %read about 3-arge ops and non-zero-based ranges.Alan Mishchenko2015-06-231-5/+15
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* Fixed a typo in variable names.Alan Mishchenko2015-02-071-9/+9
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* Added SMT parser for Wlc_Ntk_t.Alan Mishchenko2015-02-071-14/+17
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* Outputting initial state in Wlc_Ntk_t.Alan Mishchenko2015-01-251-16/+32
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* Fix in deriving the init values for Wlc_Ntk_t.Alan Mishchenko2015-01-221-0/+2
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* Support of init-state in AIGs derived from word-level designs in Wlc_Ntk_t.Alan Mishchenko2015-01-211-1/+1
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* Support of init-state in AIGs derived from word-level designs in Wlc_Ntk_t.Alan Mishchenko2015-01-211-6/+52
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* Induced bug fix in bitblasting of rotation operator.Alan Mishchenko2014-11-291-1/+2
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* Improvements to word-level network package.Alan Mishchenko2014-11-141-1/+1
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* Enabling AIGs with boxes for word-level and sequential designs.Alan Mishchenko2014-11-131-1/+1
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* Improvements to the parser.Alan Mishchenko2014-10-101-7/+86
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* Support for sequential designs in word-level Verilog.Alan Mishchenko2014-09-261-21/+81
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* Bug fix in handling MUXes in Verilog parser, induced by recent changes.Alan Mishchenko2014-09-241-0/+2
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* Added support of word-level MUXes represented as 'always'-statements.Alan Mishchenko2014-09-241-2/+95
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* Concurrency for Boolean matching.Alan Mishchenko2014-09-181-1/+1
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* Improvements to word-level Verilog parser.Alan Mishchenko2014-09-171-2/+3
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* Improvements to word-level Verilog parser.Alan Mishchenko2014-09-171-10/+17
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* Improvements to word-level Verilog parser.Alan Mishchenko2014-09-161-73/+254
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* New word-level representation package.Alan Mishchenko2014-09-121-0/+711
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