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iCE40/abc
yosys-experimental
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wlc
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wlcReadVer.c
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Author
Age
Files
Lines
*
New word-level transformation.
Alan Mishchenko
2017-03-17
1
-1
/
+1
|
*
Word-level abstraction.
Alan Mishchenko
2017-02-09
1
-1
/
+1
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*
Word-level abstraction.
Alan Mishchenko
2017-02-09
1
-1
/
+1
|
*
Commenting out debug code.
Alan Mishchenko
2017-01-29
1
-1
/
+0
|
*
Updates to arithmetic verification.
Alan Mishchenko
2017-01-29
1
-0
/
+1
|
*
Adding visualization of word-level networks Wlc_Ntk_t.
Alan Mishchenko
2017-01-26
1
-3
/
+2
|
*
Adding visualization of word-level networks Wlc_Ntk_t.
Alan Mishchenko
2017-01-26
1
-1
/
+1
|
*
Change Verilog reader to take a string rather than file name.
Alan Mishchenko
2016-10-06
1
-6
/
+8
|
*
Updates to arithmetic verification.
Alan Mishchenko
2016-08-05
1
-1
/
+1
|
*
Adding output range support to %blast.
Alan Mishchenko
2016-07-18
1
-1
/
+1
|
*
Several corner-case bugs in %read, &cec, and st.
Alan Mishchenko
2016-07-16
1
-1
/
+1
|
*
New profiling features for word-level optimizations.
Alan Mishchenko
2016-06-04
1
-1
/
+1
|
*
Improving SMT-LIB parser.
Alan Mishchenko
2016-05-23
1
-1
/
+1
|
*
Improving SMT-LIB parser.
Alan Mishchenko
2016-05-21
1
-0
/
+1
|
*
Improving SMT-LIB parser.
Alan Mishchenko
2016-05-20
1
-0
/
+3
|
*
Enabling AIGs without structural hashing.
Alan Mishchenko
2016-05-20
1
-1
/
+1
|
*
Experiments with CEC for arithmetic circuits.
Alan Mishchenko
2016-05-07
1
-0
/
+1
|
*
Supporting negative and reverse ranges of word-level variables in Wlc.
Alan Mishchenko
2016-04-04
1
-19
/
+46
|
*
Supporting bit-wise XNOR operator in Wlc_Ntk_t.
Alan Mishchenko
2016-03-18
1
-1
/
+1
|
*
Supporting complemented reduction operators.
Alan Mishchenko
2016-03-11
1
-6
/
+7
|
*
Supporting complemented reduction operators.
Alan Mishchenko
2016-03-10
1
-4
/
+14
|
*
Supporting ~^ as equality operator in Wlc.
Alan Mishchenko
2016-03-04
1
-2
/
+3
|
*
Improving bit-blasting of a multiplier and squarer.
Alan Mishchenko
2016-02-13
1
-1
/
+1
|
*
Adding support for a different bit-blasting of a multiplier and squarer.
Alan Mishchenko
2016-02-12
1
-0
/
+2
|
*
Supporting X-valued constants in Wlc_Ntk_t.
Alan Mishchenko
2016-02-02
1
-11
/
+16
|
*
Adding code to support gate profiles.
Alan Mishchenko
2015-12-14
1
-1
/
+4
|
*
Extending Verilog parser to handle 'default' in the case-statement.
Alan Mishchenko
2015-12-07
1
-11
/
+27
|
*
Making ABC error out instead of crashing when non-standard range is given.
Alan Mishchenko
2015-08-03
1
-3
/
+8
|
*
Improving Wlc_Ntk_t data-structure by extending bit-ranges up to 4B enabling ↵
Alan Mishchenko
2015-07-16
1
-1
/
+17
|
|
|
|
printout of AND2 in '%ps -d'.
*
Improved bit-blasting of various operators in Wlc_Ntk_t; added SQRT operator ↵
Alan Mishchenko
2015-07-14
1
-1
/
+3
|
|
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|
(@).
*
Bug fixing in %blast when blasting MUX coming from always-statement.
Alan Mishchenko
2015-07-07
1
-1
/
+3
|
*
Bug fixing in %blast when blasting mod operator (handling zero divisor).
Alan Mishchenko
2015-07-07
1
-1
/
+1
|
*
Add warnings to %read about 3-arge ops and non-zero-based ranges.
Alan Mishchenko
2015-06-23
1
-5
/
+15
|
*
Fixed a typo in variable names.
Alan Mishchenko
2015-02-07
1
-9
/
+9
|
*
Added SMT parser for Wlc_Ntk_t.
Alan Mishchenko
2015-02-07
1
-14
/
+17
|
*
Outputting initial state in Wlc_Ntk_t.
Alan Mishchenko
2015-01-25
1
-16
/
+32
|
*
Fix in deriving the init values for Wlc_Ntk_t.
Alan Mishchenko
2015-01-22
1
-0
/
+2
|
*
Support of init-state in AIGs derived from word-level designs in Wlc_Ntk_t.
Alan Mishchenko
2015-01-21
1
-1
/
+1
|
*
Support of init-state in AIGs derived from word-level designs in Wlc_Ntk_t.
Alan Mishchenko
2015-01-21
1
-6
/
+52
|
*
Induced bug fix in bitblasting of rotation operator.
Alan Mishchenko
2014-11-29
1
-1
/
+2
|
*
Improvements to word-level network package.
Alan Mishchenko
2014-11-14
1
-1
/
+1
|
*
Enabling AIGs with boxes for word-level and sequential designs.
Alan Mishchenko
2014-11-13
1
-1
/
+1
|
*
Improvements to the parser.
Alan Mishchenko
2014-10-10
1
-7
/
+86
|
*
Support for sequential designs in word-level Verilog.
Alan Mishchenko
2014-09-26
1
-21
/
+81
|
*
Bug fix in handling MUXes in Verilog parser, induced by recent changes.
Alan Mishchenko
2014-09-24
1
-0
/
+2
|
*
Added support of word-level MUXes represented as 'always'-statements.
Alan Mishchenko
2014-09-24
1
-2
/
+95
|
*
Concurrency for Boolean matching.
Alan Mishchenko
2014-09-18
1
-1
/
+1
|
*
Improvements to word-level Verilog parser.
Alan Mishchenko
2014-09-17
1
-2
/
+3
|
*
Improvements to word-level Verilog parser.
Alan Mishchenko
2014-09-17
1
-10
/
+17
|
*
Improvements to word-level Verilog parser.
Alan Mishchenko
2014-09-16
1
-73
/
+254
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