iCE40/abc - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
...
*	Support of init-state in AIGs derived from word-level designs in Wlc_Ntk_t.	Alan Mishchenko	2015-01-21	1	-1/+1
*	Support of init-state in AIGs derived from word-level designs in Wlc_Ntk_t.	Alan Mishchenko	2015-01-21	1	-6/+52
*	Induced bug fix in bitblasting of rotation operator.	Alan Mishchenko	2014-11-29	1	-1/+2
*	Improvements to word-level network package.	Alan Mishchenko	2014-11-14	1	-1/+1
*	Enabling AIGs with boxes for word-level and sequential designs.	Alan Mishchenko	2014-11-13	1	-1/+1
*	Improvements to the parser.	Alan Mishchenko	2014-10-10	1	-7/+86
*	Support for sequential designs in word-level Verilog.	Alan Mishchenko	2014-09-26	1	-21/+81
*	Bug fix in handling MUXes in Verilog parser, induced by recent changes.	Alan Mishchenko	2014-09-24	1	-0/+2
*	Added support of word-level MUXes represented as 'always'-statements.	Alan Mishchenko	2014-09-24	1	-2/+95
*	Concurrency for Boolean matching.	Alan Mishchenko	2014-09-18	1	-1/+1
*	Improvements to word-level Verilog parser.	Alan Mishchenko	2014-09-17	1	-2/+3
*	Improvements to word-level Verilog parser.	Alan Mishchenko	2014-09-17	1	-10/+17
*	Improvements to word-level Verilog parser.	Alan Mishchenko	2014-09-16	1	-73/+254
*	New word-level representation package.	Alan Mishchenko	2014-09-12	1	-0/+711