Commit message (Collapse) | Author | Age | Files | Lines | |
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* | Renaming DSD commands (dsd_tune -> dsd_match; dsd_clean -> dsd_filter). | Alan Mishchenko | 2014-09-28 | 1 | -1/+1 |
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* | Support for sequential designs in word-level Verilog. | Alan Mishchenko | 2014-09-26 | 1 | -9/+34 |
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* | Added support of word-level MUXes represented as 'always'-statements. | Alan Mishchenko | 2014-09-24 | 1 | -0/+24 |
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* | Improvements to word-level Verilog parser. | Alan Mishchenko | 2014-09-17 | 1 | -1/+1 |
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* | Improvements to word-level Verilog parser. | Alan Mishchenko | 2014-09-17 | 1 | -4/+86 |
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* | Improvements to word-level Verilog parser. | Alan Mishchenko | 2014-09-16 | 1 | -0/+1 |
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* | Compiler warnings. | Alan Mishchenko | 2014-09-12 | 1 | -1/+1 |
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* | New word-level representation package. | Alan Mishchenko | 2014-09-12 | 1 | -0/+204 |