iCE40/abc - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	Renaming DSD commands (dsd_tune -> dsd_match; dsd_clean -> dsd_filter).	Alan Mishchenko	2014-09-28	1	-1/+1
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*	Support for sequential designs in word-level Verilog.	Alan Mishchenko	2014-09-26	5	-79/+196
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*	Enabling print-out, for each operator, of the percetage of AND nodes after ↵	Alan Mishchenko	2014-09-25	4	-14/+35
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*	Printing node type statistics.	Alan Mishchenko	2014-09-24	1	-33/+57
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*	Printing node type statistics.	Alan Mishchenko	2014-09-24	1	-10/+10
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*	Printing node type statistics.	Alan Mishchenko	2014-09-24	2	-2/+106
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*	Bug fix in handling MUXes in Verilog parser, induced by recent changes.	Alan Mishchenko	2014-09-24	1	-0/+2
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*	Added support of word-level MUXes represented as 'always'-statements.	Alan Mishchenko	2014-09-24	1	-2/+2
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*	Added support of word-level MUXes represented as 'always'-statements.	Alan Mishchenko	2014-09-24	3	-18/+167
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*	Debugging the bit-blaster.	Alan Mishchenko	2014-09-23	1	-1/+15
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*	Debugging the bit-blaster.	Alan Mishchenko	2014-09-23	1	-7/+27
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*	Concurrency for Boolean matching.	Alan Mishchenko	2014-09-18	1	-1/+1
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*	Improvements to word-level Verilog parser.	Alan Mishchenko	2014-09-17	2	-3/+4
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*	Improvements to word-level Verilog parser.	Alan Mishchenko	2014-09-17	5	-230/+488
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*	Improvements to word-level Verilog parser.	Alan Mishchenko	2014-09-16	5	-78/+277
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*	Compiler error (duplicate typedef).	Alan Mishchenko	2014-09-15	1	-1/+0
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*	Compiler warnings.	Alan Mishchenko	2014-09-12	4	-47/+47
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*	New word-level representation package.	Alan Mishchenko	2014-09-12	8	-0/+2203