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yosys-experimental
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wlc
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Author
Age
Files
Lines
...
*
Supporting 'distinct' keyword in SMT-LIB parser.
Alan Mishchenko
2015-06-20
1
-2
/
+2
*
Adding new debugging feature to Wlc_Ntk_t.
Alan Mishchenko
2015-06-19
3
-1
/
+57
*
Bug with in signed MUX.
Alan Mishchenko
2015-06-14
1
-8
/
+11
*
Bug with in signed MUX.
Alan Mishchenko
2015-06-12
1
-2
/
+4
*
Sequential word-level simulator for Wlc_Ntk_t.
Alan Mishchenko
2015-06-04
6
-4
/
+266
*
Bug fix in %read_smt and prevent crash of &cec if there is no current AIG.
Alan Mishchenko
2015-04-27
1
-4
/
+14
*
Fix inconsistency between operators and symbols in Wlc_Ntk_t.
Alan Mishchenko
2015-04-25
2
-37
/
+38
*
Suggested fixes to compile with 'gcc -x c++'.
Alan Mishchenko
2015-04-24
1
-2
/
+2
*
Scalable SOP manipulation package.
Alan Mishchenko
2015-03-18
1
-0
/
+1
*
Several bug fixes and silencing requests.
Alan Mishchenko
2015-03-16
1
-3
/
+3
*
Support for representing programmable cell configuration data.
Alan Mishchenko
2015-03-08
1
-1
/
+1
*
Bug fix WLC package (reusing name buffer, resulting in wrong print-outs).
Alan Mishchenko
2015-03-03
1
-3
/
+2
*
Improvements to the SMTLIB parser.
Alan Mishchenko
2015-02-28
2
-533
/
+687
*
Adding fflush() to make sure stdout responses appear on time.
Alan Mishchenko
2015-02-20
1
-0
/
+2
*
Modifications to read SMTLIB file from stdin.
Alan Mishchenko
2015-02-18
1
-1
/
+0
*
Modifications to read SMTLIB file from stdin.
Alan Mishchenko
2015-02-18
2
-27
/
+18
*
Modifications to read SMTLIB file from stdin.
Alan Mishchenko
2015-02-18
1
-1
/
+1
*
Modifications to read SMTLIB file from stdin.
Alan Mishchenko
2015-02-18
6
-101
/
+264
*
Modifications to read SMTLIB file from stdin.
Alan Mishchenko
2015-02-15
5
-70
/
+214
*
Several improvements to CBA data-structure.
Alan Mishchenko
2015-02-13
1
-1
/
+0
*
Modifications to read SMTLIB file from stdin.
Alan Mishchenko
2015-02-11
4
-11
/
+75
*
Fixed a typo in variable names.
Alan Mishchenko
2015-02-07
1
-9
/
+9
*
Added SMT parser for Wlc_Ntk_t.
Alan Mishchenko
2015-02-07
6
-28
/
+725
*
Several ongoing changes.
Alan Mishchenko
2015-01-26
1
-1
/
+1
*
Outputting initial state in Wlc_Ntk_t.
Alan Mishchenko
2015-01-26
1
-28
/
+25
*
Outputting initial state in Wlc_Ntk_t.
Alan Mishchenko
2015-01-25
4
-20
/
+71
*
Fix in deriving the init values for Wlc_Ntk_t.
Alan Mishchenko
2015-01-22
1
-0
/
+2
*
Support of init-state in AIGs derived from word-level designs in Wlc_Ntk_t.
Alan Mishchenko
2015-01-21
2
-2
/
+2
*
Support of init-state in AIGs derived from word-level designs in Wlc_Ntk_t.
Alan Mishchenko
2015-01-21
4
-7
/
+72
*
Integrating barrier buffers.
Alan Mishchenko
2014-12-08
1
-1
/
+1
*
Added and verified bit-blasting of power operator.
Alan Mishchenko
2014-11-30
1
-0
/
+32
*
Induced bug fix in bitblasting of rotation operator.
Alan Mishchenko
2014-11-29
1
-1
/
+2
*
Merging two branches.
Alan Mishchenko
2014-11-17
2
-1
/
+3
|
\
|
*
Bug fix in abstracting boxes.
Alan Mishchenko
2014-11-17
2
-1
/
+3
*
|
AND/OR bug in the UIF computation.
Alan Mishchenko
2014-11-17
1
-1
/
+1
|
/
*
Improvements to word-level network package.
Alan Mishchenko
2014-11-14
1
-2
/
+2
*
Improvements to word-level network package.
Alan Mishchenko
2014-11-14
1
-2
/
+2
*
Improvements to word-level network package.
Alan Mishchenko
2014-11-14
8
-128
/
+472
*
Enabling AIGs with boxes for word-level and sequential designs.
Alan Mishchenko
2014-11-14
1
-4
/
+5
*
Enabling AIGs with boxes for word-level and sequential designs.
Alan Mishchenko
2014-11-13
5
-16
/
+151
*
Bug fix in blasting MUX with different ranges of inputs and the output.
Alan Mishchenko
2014-11-10
1
-2
/
+2
*
Improvements to the parser.
Alan Mishchenko
2014-10-10
1
-7
/
+86
*
Bug fix in the bit-blaster.
Alan Mishchenko
2014-10-10
1
-3
/
+3
*
Bug fix in Verilog writer.
Alan Mishchenko
2014-10-02
1
-8
/
+8
*
Improvements to bit-blaster.
Alan Mishchenko
2014-10-01
2
-23
/
+88
*
Improvements to bit-blaster.
Alan Mishchenko
2014-09-30
1
-1
/
+1
*
Improvements to bit-blaster.
Alan Mishchenko
2014-09-30
2
-73
/
+117
*
Renaming DSD commands (dsd_tune -> dsd_match; dsd_clean -> dsd_filter).
Alan Mishchenko
2014-09-28
1
-1
/
+1
*
Support for sequential designs in word-level Verilog.
Alan Mishchenko
2014-09-26
5
-79
/
+196
*
Enabling print-out, for each operator, of the percetage of AND nodes after bi...
Alan Mishchenko
2014-09-25
4
-14
/
+35
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