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* Modifications to read SMTLIB file from stdin.Alan Mishchenko2015-02-155-70/+214
* Several improvements to CBA data-structure.Alan Mishchenko2015-02-131-1/+0
* Modifications to read SMTLIB file from stdin.Alan Mishchenko2015-02-114-11/+75
* Fixed a typo in variable names.Alan Mishchenko2015-02-071-9/+9
* Added SMT parser for Wlc_Ntk_t.Alan Mishchenko2015-02-076-28/+725
* Several ongoing changes.Alan Mishchenko2015-01-261-1/+1
* Outputting initial state in Wlc_Ntk_t.Alan Mishchenko2015-01-261-28/+25
* Outputting initial state in Wlc_Ntk_t.Alan Mishchenko2015-01-254-20/+71
* Fix in deriving the init values for Wlc_Ntk_t.Alan Mishchenko2015-01-221-0/+2
* Support of init-state in AIGs derived from word-level designs in Wlc_Ntk_t.Alan Mishchenko2015-01-212-2/+2
* Support of init-state in AIGs derived from word-level designs in Wlc_Ntk_t.Alan Mishchenko2015-01-214-7/+72
* Integrating barrier buffers.Alan Mishchenko2014-12-081-1/+1
* Added and verified bit-blasting of power operator.Alan Mishchenko2014-11-301-0/+32
* Induced bug fix in bitblasting of rotation operator.Alan Mishchenko2014-11-291-1/+2
* Merging two branches.Alan Mishchenko2014-11-172-1/+3
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| * Bug fix in abstracting boxes.Alan Mishchenko2014-11-172-1/+3
* | AND/OR bug in the UIF computation.Alan Mishchenko2014-11-171-1/+1
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* Improvements to word-level network package.Alan Mishchenko2014-11-141-2/+2
* Improvements to word-level network package.Alan Mishchenko2014-11-141-2/+2
* Improvements to word-level network package.Alan Mishchenko2014-11-148-128/+472
* Enabling AIGs with boxes for word-level and sequential designs.Alan Mishchenko2014-11-141-4/+5
* Enabling AIGs with boxes for word-level and sequential designs.Alan Mishchenko2014-11-135-16/+151
* Bug fix in blasting MUX with different ranges of inputs and the output.Alan Mishchenko2014-11-101-2/+2
* Improvements to the parser.Alan Mishchenko2014-10-101-7/+86
* Bug fix in the bit-blaster.Alan Mishchenko2014-10-101-3/+3
* Bug fix in Verilog writer.Alan Mishchenko2014-10-021-8/+8
* Improvements to bit-blaster.Alan Mishchenko2014-10-012-23/+88
* Improvements to bit-blaster.Alan Mishchenko2014-09-301-1/+1
* Improvements to bit-blaster.Alan Mishchenko2014-09-302-73/+117
* Renaming DSD commands (dsd_tune -> dsd_match; dsd_clean -> dsd_filter).Alan Mishchenko2014-09-281-1/+1
* Support for sequential designs in word-level Verilog.Alan Mishchenko2014-09-265-79/+196
* Enabling print-out, for each operator, of the percetage of AND nodes after bi...Alan Mishchenko2014-09-254-14/+35
* Printing node type statistics.Alan Mishchenko2014-09-241-33/+57
* Printing node type statistics.Alan Mishchenko2014-09-241-10/+10
* Printing node type statistics.Alan Mishchenko2014-09-242-2/+106
* Bug fix in handling MUXes in Verilog parser, induced by recent changes.Alan Mishchenko2014-09-241-0/+2
* Added support of word-level MUXes represented as 'always'-statements.Alan Mishchenko2014-09-241-2/+2
* Added support of word-level MUXes represented as 'always'-statements.Alan Mishchenko2014-09-243-18/+167
* Debugging the bit-blaster.Alan Mishchenko2014-09-231-1/+15
* Debugging the bit-blaster.Alan Mishchenko2014-09-231-7/+27
* Concurrency for Boolean matching.Alan Mishchenko2014-09-181-1/+1
* Improvements to word-level Verilog parser.Alan Mishchenko2014-09-172-3/+4
* Improvements to word-level Verilog parser.Alan Mishchenko2014-09-175-230/+488
* Improvements to word-level Verilog parser.Alan Mishchenko2014-09-165-78/+277
* Compiler error (duplicate typedef).Alan Mishchenko2014-09-151-1/+0
* Compiler warnings.Alan Mishchenko2014-09-124-47/+47
* New word-level representation package.Alan Mishchenko2014-09-128-0/+2203