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* Adding out-of-bounds checks to AIGER readers.Alan Mishchenko2014-09-281-1/+1
* Adding features to CNF generation.Alan Mishchenko2014-09-281-6/+16
* Renaming DSD commands (dsd_tune -> dsd_match; dsd_clean -> dsd_filter).Alan Mishchenko2014-09-283-11/+51
* Support for sequential designs in word-level Verilog.Alan Mishchenko2014-09-265-79/+196
* Enabling print-out, for each operator, of the percetage of AND nodes after bi...Alan Mishchenko2014-09-254-14/+35
* Printing node type statistics.Alan Mishchenko2014-09-241-33/+57
* Printing node type statistics.Alan Mishchenko2014-09-241-10/+10
* Printing node type statistics.Alan Mishchenko2014-09-242-2/+106
* Bug fix in handling MUXes in Verilog parser, induced by recent changes.Alan Mishchenko2014-09-241-0/+2
* Added switch -t to &flow2.Alan Mishchenko2014-09-241-4/+9
* Added support of word-level MUXes represented as 'always'-statements.Alan Mishchenko2014-09-241-2/+2
* Added support of word-level MUXes represented as 'always'-statements.Alan Mishchenko2014-09-243-18/+167
* Enables dumping stats into a file.Alan Mishchenko2014-09-232-1/+15
* Extending &cec to take a single-output miter (usage of switch -d has changed!).Alan Mishchenko2014-09-231-10/+24
* Debugging the bit-blaster.Alan Mishchenko2014-09-231-1/+15
* Debugging the bit-blaster.Alan Mishchenko2014-09-232-8/+28
* Adding switch to enable SOP balancing in '&flow2'.Alan Mishchenko2014-09-211-4/+9
* Synchronizing packages.Alan Mishchenko2014-09-203-6/+6
* Updating command 'dsd_clean'.Alan Mishchenko2014-09-201-7/+29
* Tuning the flow scripts.Alan Mishchenko2014-09-201-17/+75
* Improvements to Boolean matching.Alan Mishchenko2014-09-191-22/+20
* Improvements to Boolean matching.Alan Mishchenko2014-09-181-4/+4
* Improvements to Boolean matching.Alan Mishchenko2014-09-181-14/+28
* Improving DSD manager.Alan Mishchenko2014-09-181-6/+20
* Concurrency for Boolean matching.Alan Mishchenko2014-09-183-13/+47
* Improvements to Boolean matching.Alan Mishchenko2014-09-171-4/+29
* Improvements to word-level Verilog parser.Alan Mishchenko2014-09-172-3/+4
* Improvements to word-level Verilog parser.Alan Mishchenko2014-09-175-230/+488
* Improvements to word-level Verilog parser.Alan Mishchenko2014-09-165-78/+277
* New choice computation.Alan Mishchenko2014-09-161-10/+65
* Code restructuring.Alan Mishchenko2014-09-161-0/+49
* Compiler error (duplicate typedef).Alan Mishchenko2014-09-151-1/+0
* Compiler warnings.Alan Mishchenko2014-09-124-47/+47
* Replacing tabs with spaces.Alan Mishchenko2014-09-121-1/+1
* New word-level representation package.Alan Mishchenko2014-09-1212-61/+2214
* Resetting the random seed in 'sparsify'.Alan Mishchenko2014-09-111-0/+1
* Bug fix in transferring timing info.Alan Mishchenko2014-09-092-5/+62
* Added command 'move_names'.Alan Mishchenko2014-08-281-1/+1
* Added command 'move_names'.Alan Mishchenko2014-08-282-0/+106
* Tuning LUT mapping flow.Alan Mishchenko2014-08-281-0/+1
* Tuning LUT mapping flow.Alan Mishchenko2014-08-271-1/+1
* Compiler warning.Alan Mishchenko2014-08-271-2/+2
* Tuning LUT mapping flow.Alan Mishchenko2014-08-271-0/+135
* Improvements BLIF parser.Alan Mishchenko2014-08-273-4/+130
* Improvements to DSD balancing.Alan Mishchenko2014-08-274-37/+103
* Adding commands to save/load best network.Alan Mishchenko2014-08-262-7/+166
* Improving GIA interfaces for some procedures.Alan Mishchenko2014-08-251-1/+1
* Correcting incorrect handling of timing in several &-commands.Alan Mishchenko2014-08-251-0/+116
* Improving print-out of 'dsd -p'.Alan Mishchenko2014-08-221-1/+4
* Propagating timing support to the new synthesis/mapping commands.Alan Mishchenko2014-08-201-7/+7
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