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* Merge pull request #133 from twier/inv_get_name_mangling_fixalanminko2021-08-192-9/+43
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| * Add comment to Wlc_NtkGetInv about vNamesIn's roleTobias Wiersema2021-08-191-0/+2
| * Fix typo inifity -> infinity in inv_get helpTobias Wiersema2021-08-191-1/+1
| * Add inv_get -f to read flop names from GIATobias Wiersema2021-08-192-8/+40
* | Extending &trim to trim structurally equivalent primary outputs.Alan Mishchenko2021-08-191-3/+14
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* Improving AIG to Verilog converter.Alan Mishchenko2021-08-171-3/+8
* Suggested changes to collect and pass timing information (unused variable).Alan Mishchenko2021-08-121-1/+1
* Suggested changes to collect and pass timing information (compiler issues).Alan Mishchenko2021-08-121-7/+5
* Suggested changes to collect and pass timing information.Alan Mishchenko2021-08-122-13/+64
* Making &cec support the miter circuit.Alan Mishchenko2021-08-051-0/+14
* Supporting simple operators in NDR.Alan Mishchenko2021-08-052-4/+4
* Adding node ordering options to command &dfs.Alan Mishchenko2021-08-051-22/+13
* Experiments with LUT mapping for small functions.Alan Mishchenko2021-08-021-7/+3
* Experiments with LUT mapping for small functions.Alan Mishchenko2021-08-011-1/+2
* Allow retiming to skip some logic.Alan Mishchenko2021-07-314-9/+69
* Upgrading choice computation.Alan Mishchenko2021-07-312-21/+31
* Experiments with cofactoring.Alan Mishchenko2021-07-311-6/+23
* Experimental simulation commands.Alan Mishchenko2021-07-253-65/+458
* Command to move CI/CO names.Alan Mishchenko2021-07-161-2/+3
* Command to move CI/CO names.Alan Mishchenko2021-07-162-6/+235
* Several unrelated changes.Alan Mishchenko2021-07-151-0/+67
* Experiments with LUT mapping for small functions.Alan Mishchenko2021-07-131-3/+14
* Experiments with CEC.Alan Mishchenko2021-07-101-4/+26
* Experiments with MUX decomposition.Alan Mishchenko2021-07-081-1/+55
* Adding place holder file for resub experiments.Alan Mishchenko2021-06-241-6/+7
* Experiments with LUT mapping for small functions.Alan Mishchenko2021-06-192-28/+47
* Experiments with cut computation.Alan Mishchenko2021-06-051-0/+1
* Disabled special handling of 2-input LUTs.Alan Mishchenko2021-06-031-1/+1
* Updating LUT synthesis code.Alan Mishchenko2021-05-252-35/+120
* Adding command &extract.Alan Mishchenko2021-05-182-1/+84
* Updating LUT synthesis code.Alan Mishchenko2021-05-166-64/+439
* Adding switch muxes -a to create networks of ADDs.Alan Mishchenko2021-05-153-14/+37
* Updating LUT synthesis code.Alan Mishchenko2021-05-111-14/+25
* Disable cube-sort when deriving SOPs.Alan Mishchenko2021-05-1110-19/+29
* Updating LUT synthesis code.Alan Mishchenko2021-05-112-10/+92
* Updating LUT synthesis code.Alan Mishchenko2021-05-081-2/+3
* Fixing mismatch in &cec -x which should return undecided rather than non-equi...Alan Mishchenko2021-05-081-1/+1
* Experiments with LUT mapping for small functions.Alan Mishchenko2021-05-012-4/+73
* Making sure read_bench can read nodes up to 15 inputs.Alan Mishchenko2021-04-302-5/+6
* Several changes for standard mapping.Alan Mishchenko2021-04-281-2/+4
* Passing node labels.Alan Mishchenko2021-04-263-0/+10
* Computing sum of PO support sizes.Alan Mishchenko2021-04-091-1/+2
* An option to extend the number of primary inputs.Alan Mishchenko2021-03-281-2/+32
* Compiler warnings.Alan Mishchenko2021-03-281-3/+3
* Command &iwls21test for evaluating the results of 2021 IWLS Contest.Alan Mishchenko2021-03-282-0/+184
* Adding a random seed to control randomness in 'permute' (correction).Alan Mishchenko2021-03-111-2/+2
* Adding a random seed to control randomness in 'permute'.Alan Mishchenko2021-03-111-2/+17
* Preventing command history from being overwritten by internal scripts.Alan Mishchenko2021-01-094-1/+10
* Compiler warnings.Alan Mishchenko2020-12-211-0/+1
* Adding solver type in &sat.Alan Mishchenko2020-12-161-2/+14
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