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* Command '&slice' to cut out the bottom part of the AIG.Alan Mishchenko2013-09-111-0/+60
* Small performance bug in new 'fx'.Alan Mishchenko2013-09-111-1/+1
* Updates for the new BMC engine.Alan Mishchenko2013-09-101-2/+15
* New API to return the set of all reachable states as an AIG.Alan Mishchenko2013-09-101-1/+4
* Updates for the new BMC engine.Alan Mishchenko2013-09-091-3/+52
* Improvements to the new technology mapper.Alan Mishchenko2013-09-091-1/+32
* Improvements to the &ps.Alan Mishchenko2013-09-081-2/+6
* Improvements to the new technology mapper.Alan Mishchenko2013-09-071-2/+6
* Improvements to the new technology mapper.Alan Mishchenko2013-09-071-2/+123
* Unifying parameters for the &ps command.Alan Mishchenko2013-09-052-15/+18
* Updates for the new BMC engine.Alan Mishchenko2013-09-051-6/+11
* Updates for the new BMC engine.Alan Mishchenko2013-09-051-1/+1
* Updates for the new BMC engine.Alan Mishchenko2013-09-051-6/+12
* Adding check to &sim3 for the case when the AIG is combinational.Alan Mishchenko2013-09-051-1/+5
* Improved unrolling manager.Alan Mishchenko2013-09-051-7/+7
* Added Python API status_get_vector() similar to cex_get_vector().Alan Mishchenko2013-09-042-0/+2
* Adding switch 'ps -s' to skip counting buffers/inverters as nodes.Alan Mishchenko2013-09-021-16/+10
* Adding switch 'ps -s' to skip counting buffers/inverters as nodes.Alan Mishchenko2013-09-027-13/+38
* Removing some old useless code.Alan Mishchenko2013-09-021-4/+0
* Removing some old useless code.Alan Mishchenko2013-09-029-816/+5
* Adding interpolant computation sat_solver2.Alan Mishchenko2013-09-024-11/+20
* Modify level computation to take discretized arrival times into account.Alan Mishchenko2013-09-021-3/+7
* Adding switch &get -m to import mapped network into the &-space.Alan Mishchenko2013-09-011-2/+2
* Adding switch &get -m to import mapped network into the &-space.Alan Mishchenko2013-09-014-15/+141
* Buf fixes and minor changes to the &if mapper.Alan Mishchenko2013-08-291-1/+1
* Added switch &sim -g to enable flop grouping.Alan Mishchenko2013-08-201-2/+6
* Extending 'permute' to handle user-specified flop permutation.Alan Mishchenko2013-08-163-13/+81
* Enabling LUT decomposition in two special cases.Alan Mishchenko2013-08-141-0/+5
* Enabling additional matching feature in the LUT mapper.Alan Mishchenko2013-08-121-11/+1
* Enabling additional matching feature in the LUT mapper.Alan Mishchenko2013-08-121-7/+31
* Improvements to buffering and sizing.Alan Mishchenko2013-08-092-1/+7
* Integrated buffering and sizing.Alan Mishchenko2013-08-082-0/+5
* Improvements to buffering and sizing.Alan Mishchenko2013-08-062-0/+8
* Improvements to buffering and sizing.Alan Mishchenko2013-08-061-2/+2
* Adding new (un)buffering with phase information.Alan Mishchenko2013-08-053-1/+35
* Code for parsing the transcripts.Alan Mishchenko2013-08-021-0/+18
* SAT solver with dynamic CNF loading.Alan Mishchenko2013-08-011-0/+86
* Code for parsing the transcripts.Alan Mishchenko2013-07-301-0/+124
* Parametrizing standard-cell mapper to account for the fanout delay.Alan Mishchenko2013-07-302-6/+21
* Added commands 'maxsize' and 'unbuffer'.Alan Mishchenko2013-07-291-0/+6
* Compiler warning.Alan Mishchenko2013-07-291-1/+1
* Adding support for input slew and output capacitance to timer and gate-sizer ...Alan Mishchenko2013-07-243-4/+46
* Tuning standard-cell mapping flow.Alan Mishchenko2013-07-244-17/+53
* Tuning standard-cell mapping flow.Alan Mishchenko2013-07-232-17/+29
* Bug fix and warning print.Alan Mishchenko2013-07-221-2/+42
* Improvements to post-mapping re-sizing.Alan Mishchenko2013-07-211-14/+16
* Memory leaks.Alan Mishchenko2013-07-212-9/+5
* Adding support for input slew and output capacitance to timer and gate-sizer.Alan Mishchenko2013-07-212-3/+2
* Adding support for input slew (.input_drive) and output capacitance (.output_...Alan Mishchenko2013-07-217-115/+387
* New technology mapper.Alan Mishchenko2013-07-181-4/+8