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yosys-experimental
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Author
Age
Files
Lines
*
Adding options to &flow2.
Alan Mishchenko
2014-09-29
1
-4
/
+9
*
Adding options to &flow.
Alan Mishchenko
2014-09-29
1
-4
/
+9
*
Command to rename files in the same directory.
Alan Mishchenko
2014-09-28
1
-0
/
+191
*
Adding out-of-bounds checks to AIGER readers.
Alan Mishchenko
2014-09-28
1
-1
/
+1
*
Adding features to CNF generation.
Alan Mishchenko
2014-09-28
1
-6
/
+16
*
Renaming DSD commands (dsd_tune -> dsd_match; dsd_clean -> dsd_filter).
Alan Mishchenko
2014-09-28
3
-11
/
+51
*
Support for sequential designs in word-level Verilog.
Alan Mishchenko
2014-09-26
5
-79
/
+196
*
Enabling print-out, for each operator, of the percetage of AND nodes after bi...
Alan Mishchenko
2014-09-25
4
-14
/
+35
*
Printing node type statistics.
Alan Mishchenko
2014-09-24
1
-33
/
+57
*
Printing node type statistics.
Alan Mishchenko
2014-09-24
1
-10
/
+10
*
Printing node type statistics.
Alan Mishchenko
2014-09-24
2
-2
/
+106
*
Bug fix in handling MUXes in Verilog parser, induced by recent changes.
Alan Mishchenko
2014-09-24
1
-0
/
+2
*
Added switch -t to &flow2.
Alan Mishchenko
2014-09-24
1
-4
/
+9
*
Added support of word-level MUXes represented as 'always'-statements.
Alan Mishchenko
2014-09-24
1
-2
/
+2
*
Added support of word-level MUXes represented as 'always'-statements.
Alan Mishchenko
2014-09-24
3
-18
/
+167
*
Enables dumping stats into a file.
Alan Mishchenko
2014-09-23
2
-1
/
+15
*
Extending &cec to take a single-output miter (usage of switch -d has changed!).
Alan Mishchenko
2014-09-23
1
-10
/
+24
*
Debugging the bit-blaster.
Alan Mishchenko
2014-09-23
1
-1
/
+15
*
Debugging the bit-blaster.
Alan Mishchenko
2014-09-23
2
-8
/
+28
*
Adding switch to enable SOP balancing in '&flow2'.
Alan Mishchenko
2014-09-21
1
-4
/
+9
*
Synchronizing packages.
Alan Mishchenko
2014-09-20
3
-6
/
+6
*
Updating command 'dsd_clean'.
Alan Mishchenko
2014-09-20
1
-7
/
+29
*
Tuning the flow scripts.
Alan Mishchenko
2014-09-20
1
-17
/
+75
*
Improvements to Boolean matching.
Alan Mishchenko
2014-09-19
1
-22
/
+20
*
Improvements to Boolean matching.
Alan Mishchenko
2014-09-18
1
-4
/
+4
*
Improvements to Boolean matching.
Alan Mishchenko
2014-09-18
1
-14
/
+28
*
Improving DSD manager.
Alan Mishchenko
2014-09-18
1
-6
/
+20
*
Concurrency for Boolean matching.
Alan Mishchenko
2014-09-18
3
-13
/
+47
*
Improvements to Boolean matching.
Alan Mishchenko
2014-09-17
1
-4
/
+29
*
Improvements to word-level Verilog parser.
Alan Mishchenko
2014-09-17
2
-3
/
+4
*
Improvements to word-level Verilog parser.
Alan Mishchenko
2014-09-17
5
-230
/
+488
*
Improvements to word-level Verilog parser.
Alan Mishchenko
2014-09-16
5
-78
/
+277
*
New choice computation.
Alan Mishchenko
2014-09-16
1
-10
/
+65
*
Code restructuring.
Alan Mishchenko
2014-09-16
1
-0
/
+49
*
Compiler error (duplicate typedef).
Alan Mishchenko
2014-09-15
1
-1
/
+0
*
Compiler warnings.
Alan Mishchenko
2014-09-12
4
-47
/
+47
*
Replacing tabs with spaces.
Alan Mishchenko
2014-09-12
1
-1
/
+1
*
New word-level representation package.
Alan Mishchenko
2014-09-12
12
-61
/
+2214
*
Resetting the random seed in 'sparsify'.
Alan Mishchenko
2014-09-11
1
-0
/
+1
*
Bug fix in transferring timing info.
Alan Mishchenko
2014-09-09
2
-5
/
+62
*
Added command 'move_names'.
Alan Mishchenko
2014-08-28
1
-1
/
+1
*
Added command 'move_names'.
Alan Mishchenko
2014-08-28
2
-0
/
+106
*
Tuning LUT mapping flow.
Alan Mishchenko
2014-08-28
1
-0
/
+1
*
Tuning LUT mapping flow.
Alan Mishchenko
2014-08-27
1
-1
/
+1
*
Compiler warning.
Alan Mishchenko
2014-08-27
1
-2
/
+2
*
Tuning LUT mapping flow.
Alan Mishchenko
2014-08-27
1
-0
/
+135
*
Improvements BLIF parser.
Alan Mishchenko
2014-08-27
3
-4
/
+130
*
Improvements to DSD balancing.
Alan Mishchenko
2014-08-27
4
-37
/
+103
*
Adding commands to save/load best network.
Alan Mishchenko
2014-08-26
2
-7
/
+166
*
Improving GIA interfaces for some procedures.
Alan Mishchenko
2014-08-25
1
-1
/
+1
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