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* Testing GIA with time manager.Alan Mishchenko2012-09-241-3/+3
* Testing GIA with time manager.Alan Mishchenko2012-09-233-38/+432
* Modified structural constraint extraction (unfold -s) to work for multi-outpu...Alan Mishchenko2012-09-231-2/+2
* Migrating to array-based traversal ID.Alan Mishchenko2012-09-234-77/+19
* Cleaing AIG manager by removing pointers to HAIG.Alan Mishchenko2012-09-237-199/+1
* Integrating time manager into choice computation.Alan Mishchenko2012-09-221-2/+4
* Added simplification before the concurrent call to PDR.Alan Mishchenko2012-09-201-2/+6
* Added simplification before the concurrent call to PDR.Alan Mishchenko2012-09-201-2/+2
* Added slack computation to 'stime'.Alan Mishchenko2012-09-201-0/+3
* Modified 'read' to read all types of libraries (genlib, liberty, scl).Alan Mishchenko2012-09-201-0/+2
* Modified 'read' to read all types of libraries (genlib, liberty, scl).Alan Mishchenko2012-09-202-2/+17
* Fixes to Verilog parser.Alan Mishchenko2012-09-203-3/+9
* Extending Liberty parser to handle multi-output cells.Alan Mishchenko2012-09-191-1/+1
* Extending Liberty parser to handle multi-output cells.Alan Mishchenko2012-09-194-9/+9
* Extending Liberty parser to handle multi-output cells.Alan Mishchenko2012-09-195-25/+45
* Extending BLIF parser/write to hangle multi-output cells.Alan Mishchenko2012-09-197-100/+235
* Changes to command 'upsize'.Alan Mishchenko2012-09-181-0/+3
* Fixing mismatch between declaration of the output value of Extra_CpuTime.Alan Mishchenko2012-09-181-3/+7
* Added delay multipliers to 'map'.Alan Mishchenko2012-09-161-7/+13
* Added delay multipliers to 'map'.Alan Mishchenko2012-09-162-17/+36
* Changed a few things in the refinement package of &gla.Alan Mishchenko2012-09-161-1/+1
* Restructured the code to post-process object used during refinement in &gla.Alan Mishchenko2012-09-161-11/+8
* Cleaned 'abc.c' by removing useless procedures.Alan Mishchenko2012-09-151-1689/+939
* Created new abstraction package from the code that was all over the place.Alan Mishchenko2012-09-152-470/+13
* Prepared &gla to try abstracting and proving concurrently.Alan Mishchenko2012-09-143-15/+4
* Prepared &gla to try abstracting and proving concurrently.Alan Mishchenko2012-09-141-9/+12
* Prepared &gla to try abstracting and proving concurrently.Alan Mishchenko2012-09-141-2/+18
* Scalable gate-level abstraction.Alan Mishchenko2012-09-111-9/+30
* Added -C to command line for running commands, then staying in interactive modeNiklas Een2012-09-111-28/+39
* Fixing Verilog writer's way of writing module names.Alan Mishchenko2012-09-111-1/+1
* Unified print-out of property failures produced by all engines.Alan Mishchenko2012-09-091-5/+5
* Added switch '-p' to '&gla -n' to use full proof for UNSAT core computation (...Alan Mishchenko2012-09-091-2/+6
* Started CEX minimization procedure.Alan Mishchenko2012-09-081-0/+96
* Updating &gla_refine to perform suffic refinement.Alan Mishchenko2012-09-071-4/+17
* Updating &gla_refine to perform suffic refinement.Alan Mishchenko2012-09-071-5/+18
* Integrated new fast semi-canonical form for Boolean functions up to 16 inputs.Alan Mishchenko2012-09-061-2/+2
* Integrated new fast semi-canonical form for Boolean functions up to 16 inputs.Alan Mishchenko2012-09-064-28/+70
* Added switch 'dch -r' to skip choices with structural support redundancy.Alan Mishchenko2012-09-051-2/+6
* Added error message when the user is trying 'dsat' for multi-output comb miters.Alan Mishchenko2012-09-051-2/+2
* Added new command &gla_shrink.Alan Mishchenko2012-09-042-2/+95
* Better batch mode printout.Alan Mishchenko2012-09-041-1/+1
* Enabled recording the name of the file GIA is coming from.Alan Mishchenko2012-09-042-0/+3
* Added switch &srm -A <file> for dumping SRM into a user-specified file.Alan Mishchenko2012-09-021-10/+21
* Fixing the way constants are written into mapped Verilog files.Alan Mishchenko2012-08-311-0/+5
* Handling constant nodes in gate sizing.Alan Mishchenko2012-08-301-0/+3
* New package to read/write a subset of Liberty for STA.Alan Mishchenko2012-08-291-0/+3
* Added an API to convert a multi-output PLA into a shared AIG.Alan Mishchenko2012-08-293-25/+107
* Ensured that SC mapped network is always in a topo order.Alan Mishchenko2012-08-281-1/+14
* Added buffering based on combinational merging.Alan Mishchenko2012-08-283-5/+42
* Bug fix: abstraction commands not properly updating status when dumping inter...Alan Mishchenko2012-08-283-3/+3
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