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yosys-experimental
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Age
Files
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*
Adding AIG rehashing after LUT mapping in Gia.
Alan Mishchenko
2016-04-07
1
-3
/
+0
|
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Adding AIG rehashing after LUT mapping in Gia.
Alan Mishchenko
2016-04-07
1
-3
/
+13
|
*
Supporting edges in delay-optimization in &satlut.
Alan Mishchenko
2016-04-07
1
-2
/
+2
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*
Supporting edges in delay-optimization in &satlut.
Alan Mishchenko
2016-04-07
1
-0
/
+5
|
*
Supporting edges in delay-optimization in &satlut.
Alan Mishchenko
2016-04-07
1
-6
/
+67
|
*
Supporting edge information during mapping.
Alan Mishchenko
2016-04-06
1
-2
/
+5
|
*
Supporting negative and reverse ranges of word-level variables in Wlc.
Alan Mishchenko
2016-04-04
6
-106
/
+168
|
*
Improvements to delay-optimization in &satlut.
Alan Mishchenko
2016-04-04
1
-2
/
+7
|
*
Improvements to delay-optimization in &satlut.
Alan Mishchenko
2016-04-04
1
-7
/
+12
|
*
Improvements to delay-optimization in &satlut.
Alan Mishchenko
2016-04-04
1
-5
/
+15
|
*
Improvements to delay-optimization in &satlut.
Alan Mishchenko
2016-04-03
1
-8
/
+27
|
*
Enabling native Gia visualization in &show.
Alan Mishchenko
2016-04-03
1
-5
/
+10
|
*
Allowing Cba manager to be derived from another Cba manager.
Alan Mishchenko
2016-04-02
2
-3
/
+3
|
*
Windowing for technology mapping.
Alan Mishchenko
2016-03-30
2
-7
/
+10
|
*
Bug fix in truth table reading for funcs with less than 6 vars.
Alan Mishchenko
2016-03-28
2
-2
/
+2
|
*
Sorting multiplier inputs based on the number of constant bits.
Alan Mishchenko
2016-03-24
1
-0
/
+21
|
*
Typo in operator in Wlc_Ntk_t.
Alan Mishchenko
2016-03-18
1
-1
/
+1
|
*
Supporting bit-wise XNOR operator in Wlc_Ntk_t.
Alan Mishchenko
2016-03-18
5
-3
/
+9
|
*
Supporting complemented reduction operators.
Alan Mishchenko
2016-03-11
1
-6
/
+7
|
*
Supporting complemented reduction operators.
Alan Mishchenko
2016-03-10
5
-11
/
+40
|
*
Change error to warning in 'scorr'.
Alan Mishchenko
2016-03-09
1
-2
/
+2
|
*
Supporting ~^ as equality operator in Wlc.
Alan Mishchenko
2016-03-04
1
-2
/
+3
|
*
New hierarchical TT NPN matching.
Alan Mishchenko
2016-02-26
2
-3
/
+26
|
*
Improving bit-blasting of a multiplier and squarer.
Alan Mishchenko
2016-02-13
2
-16
/
+46
|
*
Adding support for a different bit-blasting of a multiplier and squarer.
Alan Mishchenko
2016-02-13
1
-0
/
+79
|
*
Adding support for a different bit-blasting of a multiplier and squarer.
Alan Mishchenko
2016-02-12
5
-2
/
+97
|
*
Experiments with SAT-based mapping.
Alan Mishchenko
2016-02-08
1
-1
/
+1
|
*
Added recursive bit-blasting of a carry-lookahead adder.
Alan Mishchenko
2016-02-06
1
-0
/
+51
|
*
Preserving internal signal names when 'strash' is not used.
Alan Mishchenko
2016-02-03
2
-0
/
+7
|
*
Supporting X-valued constants in Wlc_Ntk_t.
Alan Mishchenko
2016-02-02
1
-1
/
+1
|
*
Supporting X-valued constants in Wlc_Ntk_t.
Alan Mishchenko
2016-02-02
1
-6
/
+13
|
*
Supporting X-valued constants in Wlc_Ntk_t.
Alan Mishchenko
2016-02-02
4
-11
/
+26
|
*
An add-on to write Verilog for circuits mapped into simple gates.
Alan Mishchenko
2016-02-01
1
-9
/
+22
|
*
Bug fix in 'aig', for the case of non-min-base SOPs.
Alan Mishchenko
2016-01-20
1
-0
/
+1
|
*
Generating sorting network as a PLA file.
Alan Mishchenko
2016-01-20
2
-3
/
+52
|
*
New command to dump LUT network.
Alan Mishchenko
2016-01-16
1
-33
/
+97
|
*
Changes to PDR to compute f-inf clauses and import invariant (or clauses) as ↵
Alan Mishchenko
2016-01-14
8
-49
/
+243
|
|
|
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a network.
*
Adding support for delay/area tradeoff.
Alan Mishchenko
2016-01-13
1
-2
/
+14
|
*
Integrating new CNF generation into &bmc.
Alan Mishchenko
2016-01-12
1
-8
/
+16
|
*
Better print-out of SOPs. Changing default of 'fx'. Updating 'satclp' to ↵
Alan Mishchenko
2016-01-12
5
-10
/
+184
|
|
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fine prine SOPs.
*
Experiments with SAT-based mapping.
Alan Mishchenko
2016-01-10
1
-0
/
+1
|
*
Adding support of candinality clause to the SAT solver.
Alan Mishchenko
2016-01-10
1
-3
/
+7
|
*
Consolidating timing manager Scl_Con_t and propagating changes.
Alan Mishchenko
2016-01-07
1
-2
/
+40
|
*
Adding switch &miter -x for XORs outputs of two word-level POs.
Alan Mishchenko
2016-01-06
1
-2
/
+25
|
*
Adding names to GIA inputs/outputs (addressing x-valued flops).
Alan Mishchenko
2015-12-22
1
-1
/
+51
|
*
Adding names to GIA inputs/outputs. Changing polarity of invariant ↵
Alan Mishchenko
2015-12-21
1
-0
/
+34
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generated by PDR.
*
Corner-case bug in invariant profiling.
Alan Mishchenko
2015-12-18
1
-0
/
+5
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*
Adding code to support gate profiles.
Alan Mishchenko
2015-12-14
4
-20
/
+46
|
*
Extending Verilog parser to handle 'default' in the case-statement.
Alan Mishchenko
2015-12-07
1
-11
/
+27
|
*
Adding code to support gate profiles.
Alan Mishchenko
2015-12-07
2
-1
/
+12
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