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* Adding AIG rehashing after LUT mapping in Gia.Alan Mishchenko2016-04-071-3/+0
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* Adding AIG rehashing after LUT mapping in Gia.Alan Mishchenko2016-04-071-3/+13
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* Supporting edges in delay-optimization in &satlut.Alan Mishchenko2016-04-071-2/+2
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* Supporting edges in delay-optimization in &satlut.Alan Mishchenko2016-04-071-0/+5
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* Supporting edges in delay-optimization in &satlut.Alan Mishchenko2016-04-071-6/+67
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* Supporting edge information during mapping.Alan Mishchenko2016-04-061-2/+5
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* Supporting negative and reverse ranges of word-level variables in Wlc.Alan Mishchenko2016-04-046-106/+168
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* Improvements to delay-optimization in &satlut.Alan Mishchenko2016-04-041-2/+7
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* Improvements to delay-optimization in &satlut.Alan Mishchenko2016-04-041-7/+12
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* Improvements to delay-optimization in &satlut.Alan Mishchenko2016-04-041-5/+15
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* Improvements to delay-optimization in &satlut.Alan Mishchenko2016-04-031-8/+27
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* Enabling native Gia visualization in &show.Alan Mishchenko2016-04-031-5/+10
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* Allowing Cba manager to be derived from another Cba manager.Alan Mishchenko2016-04-022-3/+3
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* Windowing for technology mapping.Alan Mishchenko2016-03-302-7/+10
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* Bug fix in truth table reading for funcs with less than 6 vars.Alan Mishchenko2016-03-282-2/+2
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* Sorting multiplier inputs based on the number of constant bits.Alan Mishchenko2016-03-241-0/+21
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* Typo in operator in Wlc_Ntk_t.Alan Mishchenko2016-03-181-1/+1
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* Supporting bit-wise XNOR operator in Wlc_Ntk_t.Alan Mishchenko2016-03-185-3/+9
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* Supporting complemented reduction operators.Alan Mishchenko2016-03-111-6/+7
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* Supporting complemented reduction operators.Alan Mishchenko2016-03-105-11/+40
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* Change error to warning in 'scorr'.Alan Mishchenko2016-03-091-2/+2
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* Supporting ~^ as equality operator in Wlc.Alan Mishchenko2016-03-041-2/+3
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* New hierarchical TT NPN matching.Alan Mishchenko2016-02-262-3/+26
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* Improving bit-blasting of a multiplier and squarer.Alan Mishchenko2016-02-132-16/+46
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* Adding support for a different bit-blasting of a multiplier and squarer.Alan Mishchenko2016-02-131-0/+79
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* Adding support for a different bit-blasting of a multiplier and squarer.Alan Mishchenko2016-02-125-2/+97
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* Experiments with SAT-based mapping.Alan Mishchenko2016-02-081-1/+1
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* Added recursive bit-blasting of a carry-lookahead adder.Alan Mishchenko2016-02-061-0/+51
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* Preserving internal signal names when 'strash' is not used.Alan Mishchenko2016-02-032-0/+7
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* Supporting X-valued constants in Wlc_Ntk_t.Alan Mishchenko2016-02-021-1/+1
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* Supporting X-valued constants in Wlc_Ntk_t.Alan Mishchenko2016-02-021-6/+13
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* Supporting X-valued constants in Wlc_Ntk_t.Alan Mishchenko2016-02-024-11/+26
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* An add-on to write Verilog for circuits mapped into simple gates.Alan Mishchenko2016-02-011-9/+22
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* Bug fix in 'aig', for the case of non-min-base SOPs.Alan Mishchenko2016-01-201-0/+1
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* Generating sorting network as a PLA file.Alan Mishchenko2016-01-202-3/+52
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* New command to dump LUT network.Alan Mishchenko2016-01-161-33/+97
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* Changes to PDR to compute f-inf clauses and import invariant (or clauses) as ↵Alan Mishchenko2016-01-148-49/+243
| | | | a network.
* Adding support for delay/area tradeoff.Alan Mishchenko2016-01-131-2/+14
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* Integrating new CNF generation into &bmc.Alan Mishchenko2016-01-121-8/+16
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* Better print-out of SOPs. Changing default of 'fx'. Updating 'satclp' to ↵Alan Mishchenko2016-01-125-10/+184
| | | | fine prine SOPs.
* Experiments with SAT-based mapping.Alan Mishchenko2016-01-101-0/+1
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* Adding support of candinality clause to the SAT solver.Alan Mishchenko2016-01-101-3/+7
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* Consolidating timing manager Scl_Con_t and propagating changes.Alan Mishchenko2016-01-071-2/+40
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* Adding switch &miter -x for XORs outputs of two word-level POs.Alan Mishchenko2016-01-061-2/+25
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* Adding names to GIA inputs/outputs (addressing x-valued flops).Alan Mishchenko2015-12-221-1/+51
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* Adding names to GIA inputs/outputs. Changing polarity of invariant ↵Alan Mishchenko2015-12-211-0/+34
| | | | generated by PDR.
* Corner-case bug in invariant profiling.Alan Mishchenko2015-12-181-0/+5
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* Adding code to support gate profiles.Alan Mishchenko2015-12-144-20/+46
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* Extending Verilog parser to handle 'default' in the case-statement.Alan Mishchenko2015-12-071-11/+27
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* Adding code to support gate profiles.Alan Mishchenko2015-12-072-1/+12
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