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* New command &stochsyn for stochastic synthesis.Alan Mishchenko2021-10-061-0/+103
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* Other compiler changes.Alan Mishchenko2021-09-261-0/+7
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* Changing declaration of Vec_Ptr_t sorting function to satisfy some compilers.Alan Mishchenko2021-09-2614-20/+20
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* Two rare corner-case bugs in &if mapper.Alan Mishchenko2021-09-261-1/+5
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* Adding command &reshape.Alan Mishchenko2021-09-211-6/+11
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* Adding command &reshape.Alan Mishchenko2021-09-212-21/+63
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* Removing unused command.Alan Mishchenko2021-09-212-157/+0
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* Various changes.Alan Mishchenko2021-09-213-13/+23
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* Improving MiniAIG and name manager.Alan Mishchenko2021-09-161-1/+1
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* Further debugging of MiniLUT APIs.Alan Mishchenko2021-09-161-0/+1
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* Various changes.Alan Mishchenko2021-09-141-9/+16
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* Enable command 'pipe' for pipelining.Alan Mishchenko2021-09-133-15/+15
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* Disabling command print_mint when CUDD is not used.Alan Mishchenko2021-09-071-0/+7
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* Bug fix in the timing manager.Alan Mishchenko2021-09-061-28/+30
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* Various changes.Alan Mishchenko2021-09-042-2/+2
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* Additional MiniLUT API.Alan Mishchenko2021-09-031-0/+1
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* Various changes.Alan Mishchenko2021-09-023-7/+278
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* Allow &mfs to work on sequential AIGs.Alan Mishchenko2021-08-241-1/+10
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* Compiler warnings.Alan Mishchenko2021-08-235-5/+7
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* Adding input/output/flop name reading in command &r.Alan Mishchenko2021-08-221-0/+39
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* Support of pair-wise miter and other changes.Alan Mishchenko2021-08-222-4/+21
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* Merge pull request #133 from twier/inv_get_name_mangling_fixalanminko2021-08-192-9/+43
|\ | | | | Fix name-mangling behavior of inv_get
| * Add comment to Wlc_NtkGetInv about vNamesIn's roleTobias Wiersema2021-08-191-0/+2
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| * Fix typo inifity -> infinity in inv_get helpTobias Wiersema2021-08-191-1/+1
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| * Add inv_get -f to read flop names from GIATobias Wiersema2021-08-192-8/+40
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* | Extending &trim to trim structurally equivalent primary outputs.Alan Mishchenko2021-08-191-3/+14
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* Improving AIG to Verilog converter.Alan Mishchenko2021-08-171-3/+8
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* Suggested changes to collect and pass timing information (unused variable).Alan Mishchenko2021-08-121-1/+1
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* Suggested changes to collect and pass timing information (compiler issues).Alan Mishchenko2021-08-121-7/+5
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* Suggested changes to collect and pass timing information.Alan Mishchenko2021-08-122-13/+64
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* Making &cec support the miter circuit.Alan Mishchenko2021-08-051-0/+14
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* Supporting simple operators in NDR.Alan Mishchenko2021-08-052-4/+4
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* Adding node ordering options to command &dfs.Alan Mishchenko2021-08-051-22/+13
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* Experiments with LUT mapping for small functions.Alan Mishchenko2021-08-021-7/+3
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* Experiments with LUT mapping for small functions.Alan Mishchenko2021-08-011-1/+2
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* Allow retiming to skip some logic.Alan Mishchenko2021-07-314-9/+69
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* Upgrading choice computation.Alan Mishchenko2021-07-312-21/+31
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* Experiments with cofactoring.Alan Mishchenko2021-07-311-6/+23
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* Experimental simulation commands.Alan Mishchenko2021-07-253-65/+458
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* Command to move CI/CO names.Alan Mishchenko2021-07-161-2/+3
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* Command to move CI/CO names.Alan Mishchenko2021-07-162-6/+235
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* Several unrelated changes.Alan Mishchenko2021-07-151-0/+67
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* Experiments with LUT mapping for small functions.Alan Mishchenko2021-07-131-3/+14
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* Experiments with CEC.Alan Mishchenko2021-07-101-4/+26
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* Experiments with MUX decomposition.Alan Mishchenko2021-07-081-1/+55
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* Adding place holder file for resub experiments.Alan Mishchenko2021-06-241-6/+7
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* Experiments with LUT mapping for small functions.Alan Mishchenko2021-06-192-28/+47
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* Experiments with cut computation.Alan Mishchenko2021-06-051-0/+1
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* Disabled special handling of 2-input LUTs.Alan Mishchenko2021-06-031-1/+1
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* Updating LUT synthesis code.Alan Mishchenko2021-05-252-35/+120
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