summaryrefslogtreecommitdiffstats
path: root/src/base
Commit message (Expand)AuthorAgeFilesLines
* Adding switch &qbf -q to quantify functional variables.Alan Mishchenko2014-10-201-2/+20
* Improved QBF solver.Alan Mishchenko2014-10-181-2/+125
* Fixed "bm" command hang issue.grigora2014-10-111-7/+6
* Improvements to the parser.Alan Mishchenko2014-10-101-7/+86
* Naive (SAT-only) CEC option.Alan Mishchenko2014-10-101-2/+6
* Bug fix in the bit-blaster.Alan Mishchenko2014-10-101-3/+3
* Improvements to ISOP.Alan Mishchenko2014-10-102-5/+7
* Improvements to ISOP.Alan Mishchenko2014-10-102-4/+10
* Detection of threshold functions.Alan Mishchenko2014-10-082-3/+25
* Bug fix in move_names.Alan Mishchenko2014-10-051-0/+1
* Deriving cell mapping with &if -kz.Alan Mishchenko2014-10-041-1/+6
* Deriving cell mapping with &if -kz.Alan Mishchenko2014-10-041-1/+14
* Deriving AIG after cell mapping.Alan Mishchenko2014-10-032-2/+29
* Bug fix in Verilog writer.Alan Mishchenko2014-10-021-8/+8
* Adding switch -R to 'if'.Alan Mishchenko2014-10-021-27/+39
* Improvements to bit-blaster.Alan Mishchenko2014-10-012-23/+88
* Improvements to bit-blaster.Alan Mishchenko2014-09-301-1/+1
* Improvements to bit-blaster.Alan Mishchenko2014-09-303-75/+120
* Adding options to &flow.Alan Mishchenko2014-09-291-4/+9
* Adding options to &flow2.Alan Mishchenko2014-09-291-4/+9
* Adding options to &flow.Alan Mishchenko2014-09-291-4/+9
* Command to rename files in the same directory.Alan Mishchenko2014-09-281-0/+191
* Adding out-of-bounds checks to AIGER readers.Alan Mishchenko2014-09-281-1/+1
* Adding features to CNF generation.Alan Mishchenko2014-09-281-6/+16
* Renaming DSD commands (dsd_tune -> dsd_match; dsd_clean -> dsd_filter).Alan Mishchenko2014-09-283-11/+51
* Support for sequential designs in word-level Verilog.Alan Mishchenko2014-09-265-79/+196
* Enabling print-out, for each operator, of the percetage of AND nodes after bi...Alan Mishchenko2014-09-254-14/+35
* Printing node type statistics.Alan Mishchenko2014-09-241-33/+57
* Printing node type statistics.Alan Mishchenko2014-09-241-10/+10
* Printing node type statistics.Alan Mishchenko2014-09-242-2/+106
* Bug fix in handling MUXes in Verilog parser, induced by recent changes.Alan Mishchenko2014-09-241-0/+2
* Added switch -t to &flow2.Alan Mishchenko2014-09-241-4/+9
* Added support of word-level MUXes represented as 'always'-statements.Alan Mishchenko2014-09-241-2/+2
* Added support of word-level MUXes represented as 'always'-statements.Alan Mishchenko2014-09-243-18/+167
* Enables dumping stats into a file.Alan Mishchenko2014-09-232-1/+15
* Extending &cec to take a single-output miter (usage of switch -d has changed!).Alan Mishchenko2014-09-231-10/+24
* Debugging the bit-blaster.Alan Mishchenko2014-09-231-1/+15
* Debugging the bit-blaster.Alan Mishchenko2014-09-232-8/+28
* Adding switch to enable SOP balancing in '&flow2'.Alan Mishchenko2014-09-211-4/+9
* Synchronizing packages.Alan Mishchenko2014-09-203-6/+6
* Updating command 'dsd_clean'.Alan Mishchenko2014-09-201-7/+29
* Tuning the flow scripts.Alan Mishchenko2014-09-201-17/+75
* Improvements to Boolean matching.Alan Mishchenko2014-09-191-22/+20
* Improvements to Boolean matching.Alan Mishchenko2014-09-181-4/+4
* Improvements to Boolean matching.Alan Mishchenko2014-09-181-14/+28
* Improving DSD manager.Alan Mishchenko2014-09-181-6/+20
* Concurrency for Boolean matching.Alan Mishchenko2014-09-183-13/+47
* Improvements to Boolean matching.Alan Mishchenko2014-09-171-4/+29
* Improvements to word-level Verilog parser.Alan Mishchenko2014-09-172-3/+4
* Improvements to word-level Verilog parser.Alan Mishchenko2014-09-175-230/+488
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-02 15:51:18 +0000