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* Temporary bug fix for signal names in WLC (correction).Alan Mishchenko2018-03-211-2/+5
* Temporary bug fix for signal names in WLC.Alan Mishchenko2018-03-211-0/+2
* Bug fix in blasting with boxes.Alan Mishchenko2018-03-061-1/+1
* Extending primitives supported by WLC.Alan Mishchenko2018-03-033-5/+85
* Adding parameters and improvements to %blast.Alan Mishchenko2018-02-286-1/+20
* Adding parameters and improvements to %blast.Alan Mishchenko2018-02-289-98/+296
* Adding support for adders with carry-in in WLC and NDR.Alan Mishchenko2018-02-244-5/+15
* Bug fix in NDR handling.Alan Mishchenko2018-02-201-6/+38
* Compilation problem with pow().Alan Mishchenko2018-02-192-2/+2
* Extending MiniLUT to return attributes.Alan Mishchenko2018-02-111-0/+1
* Experiments with LUT mapping.Alan Mishchenko2018-02-101-5/+18
* Fixing input swapping issue in MUXes derived from NDR.Alan Mishchenko2018-02-072-0/+4
* Improvements to NDR to represent hierarchical designs.Alan Mishchenko2018-02-051-2/+1
* Improvements to NDR to represent hierarchical designs.Alan Mishchenko2018-02-053-19/+21
* Adding support of reading and writing designs using a new internal format (bu...Alan Mishchenko2018-01-291-18/+76
* Adding support of reading and writing designs using a new internal format.Alan Mishchenko2018-01-284-4/+362
* Experiments with circuit-based SAT.Alan Mishchenko2018-01-271-4/+15
* Experiments with SAT-based simulation.Alan Mishchenko2018-01-251-1/+1
* Updates to exact synthesis commands.Alan Mishchenko2018-01-191-4/+26
* New command 'testexact'.Alan Mishchenko2018-01-041-0/+51
* New exact synthesis command 'allexact'.Alan Mishchenko2017-12-301-2/+2
* New exact synthesis command 'allexact'.Alan Mishchenko2017-12-281-1/+170
* Bug fix in 'write_aiger_cex'.Alan Mishchenko2017-12-201-0/+1
* Adding parameter structure to 'twoexact' and 'lutexact'.Alan Mishchenko2017-12-061-59/+71
* An improvement to 'twoexact' and 'lutexact'.Alan Mishchenko2017-12-061-0/+27
* An improvement to 'twoexact' and 'lutexact'.Alan Mishchenko2017-12-061-2/+2
* Switch -a to use only AND-gates in 'twoexact' and 'lutexact'.Alan Mishchenko2017-12-061-14/+22
* New command 'lutexact'.Alan Mishchenko2017-12-051-0/+104
* Adding switch -a to 'write_verilog' to write factored forms without XORs and ...Alan Mishchenko2017-12-035-17/+30
* Portability changes for gcc-6 suggested by Clifford.Alan Mishchenko2017-12-031-5/+0
* Portability changes for gcc-6 suggested by Clifford.Alan Mishchenko2017-12-021-2/+2
* Portability changes for gcc-6 suggested by Clifford.Alan Mishchenko2017-12-021-1/+6
* C++ comaptibility: add namespace support to GlucoseBaruch Sterin2017-11-231-0/+2
* C++ compatibility: fix bad pointer comparisonBaruch Sterin2017-11-231-1/+1
* Changes to make GIA structural hashing use a dedicated array instead of pObj-...Alan Mishchenko2017-11-131-2/+2
* Profiling quantification and other changes.Alan Mishchenko2017-11-061-0/+61
* Adding API to dump MiniAIG into a Verilog file and other small changes.Alan Mishchenko2017-10-225-2/+10
* Adding random search in exact synthesis.Alan Mishchenko2017-10-201-6/+23
* Integrating old SAT solver into majexact and twoexact.Alan Mishchenko2017-10-191-11/+27
* Integrating Glucose into &qbf.Alan Mishchenko2017-10-171-6/+11
* Fix the build.Alan Mishchenko2017-10-111-1/+0
* Another variation on exact synthesis.Alan Mishchenko2017-10-111-1/+80
* Improvements to SAT based SOP computation.Alan Mishchenko2017-10-061-1/+3
* Improvements to truth table manipulation.Alan Mishchenko2017-10-051-2/+2
* Fixing minimize_assuptions using Glucose.Alan Mishchenko2017-10-021-0/+1
* Adding printout of slack distribution for mapped networks.Alan Mishchenko2017-10-021-3/+7
* Exact synthesis of majority gates.Alan Mishchenko2017-10-011-14/+18
* Exact synthesis of majority gates.Alan Mishchenko2017-10-011-0/+75
* Maintenance and updates.Alan Mishchenko2017-09-242-5/+10
* Maintenance and updates.Alan Mishchenko2017-09-201-11/+22
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