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yosys-experimental
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Age
Files
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*
Improvements in bit-blasting of adders and multipliers.
Alan Mishchenko
2018-06-08
1
-8
/
+200
|
*
Adding switch 'clp -o' to reverse initial variable ordering.
Alan Mishchenko
2018-06-07
17
-36
/
+41
|
*
Experiments with path enumeration.
Alan Mishchenko
2018-06-06
1
-1
/
+1
|
*
Supporting the decoder primitive in NDR and bit-blasting.
Alan Mishchenko
2018-06-05
6
-4
/
+68
|
*
Exposing a switch to generate carry-lookahead adder during bit-blasting.
Alan Mishchenko
2018-06-05
3
-15
/
+60
|
*
Adding command print_mint.
Alan Mishchenko
2018-06-04
1
-0
/
+64
|
*
Supporting SEL in bit-blasting.
Alan Mishchenko
2018-05-25
1
-2
/
+22
|
*
Supporting NMUX and SEL in NDR.
Alan Mishchenko
2018-05-24
4
-2
/
+33
|
*
Simple BDD package.
Alan Mishchenko
2018-05-23
1
-1
/
+3
|
*
Bug fix in supporting signed multiplication in NDR.
Alan Mishchenko
2018-05-18
1
-6
/
+7
|
*
Supporting wide MUX in NDR.
Alan Mishchenko
2018-05-16
1
-2
/
+7
|
*
Bug fix in the naming of outputs in %blast -d.
Alan Mishchenko
2018-05-10
1
-3
/
+21
|
*
Bug fix in &sat -x.
Alan Mishchenko
2018-05-07
1
-2
/
+3
|
*
Adding &sat -x to save CEXes for multi-output combinational miters.
Alan Mishchenko
2018-05-06
1
-4
/
+33
|
*
Updates to NDR format (bug fixes).
Alan Mishchenko
2018-05-03
2
-11
/
+10
|
*
Updates to NDR format (flops, memories, signed mult, etc).
Alan Mishchenko
2018-04-29
8
-39
/
+352
|
*
The ECO code (fix to the broken build).
Alan Mishchenko
2018-04-28
1
-2
/
+2
|
*
Adding switch &w -p to dump AIG in a Verilog file.
Alan Mishchenko
2018-04-25
1
-2
/
+9
|
*
The ECO code.
Alan Mishchenko
2018-04-25
1
-2
/
+11
|
*
The ECO code.
Alan Mishchenko
2018-04-25
2
-8
/
+2500
|
*
Typo in the command description.
Alan Mishchenko
2018-04-25
1
-5
/
+5
|
*
Memory abstraction.
Alan Mishchenko
2018-04-20
4
-10
/
+20
|
*
Memory abstraction.
Alan Mishchenko
2018-04-19
4
-154
/
+284
|
*
Memory abstraction.
Alan Mishchenko
2018-04-15
8
-84
/
+1086
|
*
Integrating SAT-based CEX minimization (bug fix).
Alan Mishchenko
2018-03-25
1
-2
/
+2
|
*
Integrating SAT-based CEX minimization.
Alan Mishchenko
2018-03-25
1
-8
/
+20
|
*
Adding new NPN code developed by XueGong Zhou at Fudan University.
Alan Mishchenko
2018-03-25
2
-7
/
+29
|
*
Adding switch 'scorr -f' to dump inductive invariant as an AIG.
Alan Mishchenko
2018-03-22
1
-5
/
+14
|
*
Temporary bug fix for signal names in WLC (correction).
Alan Mishchenko
2018-03-21
1
-2
/
+5
|
*
Temporary bug fix for signal names in WLC.
Alan Mishchenko
2018-03-21
1
-0
/
+2
|
*
Bug fix in blasting with boxes.
Alan Mishchenko
2018-03-06
1
-1
/
+1
|
*
Extending primitives supported by WLC.
Alan Mishchenko
2018-03-03
3
-5
/
+85
|
*
Adding parameters and improvements to %blast.
Alan Mishchenko
2018-02-28
6
-1
/
+20
|
*
Adding parameters and improvements to %blast.
Alan Mishchenko
2018-02-28
9
-98
/
+296
|
*
Adding support for adders with carry-in in WLC and NDR.
Alan Mishchenko
2018-02-24
4
-5
/
+15
|
*
Bug fix in NDR handling.
Alan Mishchenko
2018-02-20
1
-6
/
+38
|
*
Compilation problem with pow().
Alan Mishchenko
2018-02-19
2
-2
/
+2
|
*
Extending MiniLUT to return attributes.
Alan Mishchenko
2018-02-11
1
-0
/
+1
|
*
Experiments with LUT mapping.
Alan Mishchenko
2018-02-10
1
-5
/
+18
|
*
Fixing input swapping issue in MUXes derived from NDR.
Alan Mishchenko
2018-02-07
2
-0
/
+4
|
*
Improvements to NDR to represent hierarchical designs.
Alan Mishchenko
2018-02-05
1
-2
/
+1
|
*
Improvements to NDR to represent hierarchical designs.
Alan Mishchenko
2018-02-05
3
-19
/
+21
|
*
Adding support of reading and writing designs using a new internal format ↵
Alan Mishchenko
2018-01-29
1
-18
/
+76
|
|
|
|
(bug fix).
*
Adding support of reading and writing designs using a new internal format.
Alan Mishchenko
2018-01-28
4
-4
/
+362
|
*
Experiments with circuit-based SAT.
Alan Mishchenko
2018-01-27
1
-4
/
+15
|
*
Experiments with SAT-based simulation.
Alan Mishchenko
2018-01-25
1
-1
/
+1
|
*
Updates to exact synthesis commands.
Alan Mishchenko
2018-01-19
1
-4
/
+26
|
*
New command 'testexact'.
Alan Mishchenko
2018-01-04
1
-0
/
+51
|
*
New exact synthesis command 'allexact'.
Alan Mishchenko
2017-12-30
1
-2
/
+2
|
*
New exact synthesis command 'allexact'.
Alan Mishchenko
2017-12-28
1
-1
/
+170
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