| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | New word-level representation package. | Alan Mishchenko | 2014-09-12 | 12 | -61/+2214 |
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| * | Resetting the random seed in 'sparsify'. | Alan Mishchenko | 2014-09-11 | 1 | -0/+1 |
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| * | Bug fix in transferring timing info. | Alan Mishchenko | 2014-09-09 | 2 | -5/+62 |
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| * | Added command 'move_names'. | Alan Mishchenko | 2014-08-28 | 1 | -1/+1 |
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| * | Added command 'move_names'. | Alan Mishchenko | 2014-08-28 | 2 | -0/+106 |
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| * | Tuning LUT mapping flow. | Alan Mishchenko | 2014-08-28 | 1 | -0/+1 |
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| * | Tuning LUT mapping flow. | Alan Mishchenko | 2014-08-27 | 1 | -1/+1 |
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| * | Compiler warning. | Alan Mishchenko | 2014-08-27 | 1 | -2/+2 |
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| * | Tuning LUT mapping flow. | Alan Mishchenko | 2014-08-27 | 1 | -0/+135 |
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| * | Improvements BLIF parser. | Alan Mishchenko | 2014-08-27 | 3 | -4/+130 |
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| * | Improvements to DSD balancing. | Alan Mishchenko | 2014-08-27 | 4 | -37/+103 |
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| * | Adding commands to save/load best network. | Alan Mishchenko | 2014-08-26 | 2 | -7/+166 |
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| * | Improving GIA interfaces for some procedures. | Alan Mishchenko | 2014-08-25 | 1 | -1/+1 |
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| * | Correcting incorrect handling of timing in several &-commands. | Alan Mishchenko | 2014-08-25 | 1 | -0/+116 |
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| * | Improving print-out of 'dsd -p'. | Alan Mishchenko | 2014-08-22 | 1 | -1/+4 |
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| * | Propagating timing support to the new synthesis/mapping commands. | Alan Mishchenko | 2014-08-20 | 1 | -7/+7 |
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| * | Extended command &cone to extract timing critical cones. | Alan Mishchenko | 2014-08-19 | 1 | -13/+51 |
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| * | Added command 'sparsify' to derive ISF from CSF. | Alan Mishchenko | 2014-08-18 | 2 | -0/+212 |
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| * | Changing default CNF generation in &bmc. | Alan Mishchenko | 2014-08-18 | 1 | -1/+1 |
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| * | Added DSD-based collapsing &dsd. | Alan Mishchenko | 2014-08-16 | 1 | -1/+1 |
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| * | Adding specialized matching to 'if'. | Alan Mishchenko | 2014-08-16 | 1 | -0/+2 |
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| * | Added DSD-based collapsing &dsd. | Alan Mishchenko | 2014-08-16 | 2 | -1/+55 |
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| * | Enabling circuit solver in &fraig. | Alan Mishchenko | 2014-08-12 | 1 | -2/+6 |
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| * | Bug fix in &fraig -L <num>. | Alan Mishchenko | 2014-08-12 | 1 | -2/+2 |
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| * | Bug fix in &fraig -L <num>. | Alan Mishchenko | 2014-08-12 | 1 | -2/+2 |
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| * | Adding delay optimization to synthesis script &syn2. | Alan Mishchenko | 2014-08-08 | 1 | -15/+30 |
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| * | Enabling cofactoring in the mapper. | Alan Mishchenko | 2014-08-06 | 1 | -2/+22 |
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| * | Enabling ISOP-based minimization in 'collapse' if EXDC is available. | Alan Mishchenko | 2014-08-04 | 2 | -2/+35 |
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| * | Profiling code for SOP/DSD/LMS balancing. | Alan Mishchenko | 2014-08-02 | 1 | -0/+20 |
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| * | Changes to the hopelessly limited Verilog parser to skip one-bit bit-ranges, ↵ | Alan Mishchenko | 2014-08-02 | 1 | -4/+26 |
| | | | | | such as [7:7], which seems to help in some cases. | ||||
| * | Small changes. | Alan Mishchenko | 2014-07-29 | 2 | -3/+4 |
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| * | Adding support for standard-cell mapping. | Alan Mishchenko | 2014-07-28 | 3 | -0/+119 |
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| * | Generating abstraction of standard cell library. | Alan Mishchenko | 2014-07-26 | 1 | -0/+189 |
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| * | Generating abstraction of standard cell library. | Alan Mishchenko | 2014-07-25 | 1 | -9/+14 |
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| * | Bug fix in 'print_gates' due to the mix-up of the inverter. | Alan Mishchenko | 2014-07-22 | 1 | -1/+1 |
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| * | Small changes. | Alan Mishchenko | 2014-07-21 | 1 | -7/+9 |
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| * | Adding new command &sopb for resource-aware SOP balancing. | Alan Mishchenko | 2014-07-21 | 1 | -34/+107 |
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| * | Updates and changes to several packages. | Alan Mishchenko | 2014-07-20 | 2 | -11/+41 |
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| * | Small changes in several packages. | Alan Mishchenko | 2014-07-17 | 1 | -1/+1 |
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| * | Improvements to profiling and printing statistics. | Alan Mishchenko | 2014-07-09 | 1 | -6/+16 |
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| * | Improvements to false path detection. | Alan Mishchenko | 2014-07-08 | 1 | -1/+1 |
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| * | Improvements to representation of choices. | Alan Mishchenko | 2014-07-01 | 1 | -3/+7 |
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| * | Changes to align node IDs in Abc_Ntk_t representing a logic network with ↵ | Alan Mishchenko | 2014-06-30 | 1 | -14/+12 |
| | | | | | Abc_Ntk_t representing an AIG, by skipping object ID number 0 reserved for the constant node. | ||||
| * | Changes to align node IDs in Abc_Ntk_t representing a logic network with ↵ | Alan Mishchenko | 2014-06-30 | 1 | -10/+14 |
| | | | | | Abc_Ntk_t representing an AIG, by skipping object ID number 0 reserved for the constant node. | ||||
| * | Changes and improvements to different packages. | Alan Mishchenko | 2014-06-28 | 1 | -1/+1 |
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| * | Changes and improvements to different packages. | Alan Mishchenko | 2014-06-28 | 1 | -6/+16 |
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| * | Changes and improvements to different packages. | Alan Mishchenko | 2014-06-26 | 1 | -0/+3 |
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| * | Improvements to power-aware mapping. | Alan Mishchenko | 2014-06-23 | 2 | -8/+17 |
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| * | Improvements to CNF generation. | Alan Mishchenko | 2014-06-23 | 1 | -1/+1 |
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| * | Improvements to CNF generation. | Alan Mishchenko | 2014-06-23 | 3 | -12/+55 |
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